AN 893: Hierarchical Partial Reconfiguration Tutorial: for Intel Cyclone® 10 GX FPGA Development Board

ID 683548
Date 7/15/2019

Updating the Top-Level Design

To update the file with the PR_IP instance:
  1. To add the PR_IP instance to the top-level design, uncomment the following code block in the file:
    pr_ip u_pr_ip
            .clk           (clock),
            .nreset        (1'b1),
            .freeze        (freeze),
            .pr_start      (1'b0),            // ignored for JTAG
            .status        (pr_ip_status),
            .data          (16'b0),
            .data_valid    (1'b0),
            .data_ready    ()
  2. To force the output ports to logic 1 during reconfiguration, use the freeze control signal output from PR_IP. However, to observe continuous blinking of the LED from the parent PR partition while PR programming the child partition, the freeze control signal does not turn off led_two_on. Ensure that the pr_led_two_on is directly assigned to led_two_on_w. led_three_on_w must choose between logic 1 and pr_led_three_on, based on the freeze signal. Uncomment the following lines of code:
    assign led_two_on_w = ? 1'b1 : pr_led_two_on;
    assign led_three_on_w = freeze ? 1'b1 : pr_led_three_on;
  3. To assign an instance of the default parent persona (blinking_led), update the file with the following block of code:
    blinking_led u_blinking_led
          .clock         (clock),
          .counter       (count_d),
          .led_two_on    (pr_led_two_on),
          .led_three_on  (pr_led_three_on)
Figure 10. Partial Reconfiguration IP Core Integration