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Step 1: Getting Started
Step 2: Creating a Child Level Sub-module
Step 3: Creating Design Partitions
Step 4: Allocating Placement and Routing Region for PR Partitions
Step 5: Adding the Partial Reconfiguration Controller IP
Step 6: Defining Personas
Step 7: Creating Revisions
Step 8: Compiling the Base Revision
Step 9: Preparing the PR Implementation Revisions for Parent PR Partition
Step 10: Preparing the PR Implementation Revisions for Child PR Partitions
Step 11: Programming the Board
Modifying an Existing Persona
Adding a New Persona to the Design
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Document Revision History for Hierarchical Partial Reconfiguration Tutorial for Intel Cyclone® 10 GX FPGA Development Board
Document Version | Intel® Quartus® Prime Version | Changes |
---|---|---|
2019.07.15 | 19.1.0 | First release of document. |