AN 893: Hierarchical Partial Reconfiguration Tutorial: for Intel Cyclone® 10 GX FPGA Development Board

ID 683548
Date 7/15/2019

Programming the Child PR Region

You must ensure that you program the correct child persona to match the parent persona.
Running the prpof_id_mif_gen.tcl script before and after the base revision compile checks for incompatible bitstreams for Intel Cyclone® 10 devices, and outputs a PR_ERROR message for incorrect bitstreams. The following errors are possible unless you run the scripts as the tutorial describes:
  • Successful PR programming, but corrupted FPGA functionality
  • Unsuccessful PR programming, and corrupted FPGA functionality
If you wish to reprogram a child PR region on the FPGA, ensure that the child PR .rbf generates from an implementation revision compile whose parent PR persona matches the persona currently on the FPGA. For example, when you program the base blinking_led.sof onto the FPGA, the parent PR persona is default. The child PR persona is default as well. To change the child PR persona to the slow persona, you have the choice of using the following bitstreams:
  1. hpr_child_slow.pr_parent_partition.pr_partition.rbf
  2. hpr_parent_slow_child_slow.pr_parent_partition.pr_partition.rbf
In this case, you must choose hpr_child_slow.pr_parent_partition.pr_partition.rbf , as this file is generated by an implementation revision that has the default parent persona. Choosing hpr_parent_slow_child_slow.pr_parent_partition.pr_partition.rbf results in unsuccessful PR programming, corrupted FPGA functionality, or both.