Visible to Intel only — GUID: nik1412473923794
Ixiasoft
Visible to Intel only — GUID: nik1412473923794
Ixiasoft
1.10. Using SignalTap II
The tx_st_ready0 and rx_st_valid0 are indications of link utilization and throughput. In the transmit direction, the frequent deassertion of the tx_st_ready0 signal typically indicates that the IP core is not receiving enough credits from the device at the far end of the PCI Express link. It could also indicate that a x4 link has trained to x1. In the receive direction, the deassertion of rx_st_valid0 indicates that the IP core is not receiving enough data.
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