L-Tile and H-Tile Avalon® Memory-mapped+ Intel® FPGA IP for PCI Express* User Guide

ID 683527
Date 9/13/2024
Public
Document Table of Contents

D.2.1.5.1. Displaying PLL Lock and Calibration Status Registers

  1. Run the following System Console Tcl commands to display the lock and the calibration status for the PLLs and channels.

    % source TCL/setup_adme.tcl

    % source TCL/xcvr_pll_suite.tcl

  2. Here are sample transcripts:
    ##########################################
    #####         ATXPLL  Status         #####
    ##########################################
    ATXPLL is Locked
    ATXPLL Calibration is Done
    ##########################################
    #####          FPLL  Status          #####
    ##########################################
    FPLL is Locked
    FPLL Calibration is Done
    ##########################################
    #####       Channel# 0 Status        #####
    ##########################################
    Channel#0 CDR is Locked to Data
    Channel#0 CDR is Locked to Reference Clock
    Channel#0 TX Calibration is Done
    Channel#0 RX Calibration is Done
    ##########################################
    ...
    ##########################################
    Channel#7 CDR is Locked to Data
    Channel#7 CDR is Locked to Reference Clock
    Channel#7 TX Calibration is Done
    Channel#7 RX Calibration is Done