L-Tile and H-Tile Avalon® Memory-mapped+ Intel® FPGA IP for PCI Express* User Guide

ID 683527
Date 3/05/2024
Public
Document Table of Contents

6.1.4. Intel Defined VSEC Capability Header

The figure below shows the address map and layout of the Intel defined VSEC Capability.
Figure 25. Vendor-Specific Extended Capability Address Map and Register Layout
Table 52.   Intel-Defined VSEC Capability Header - 0xB80

Bits

Register Description

Default Value

Access

[31:20] Next Capability Pointer: Value is the starting address of the next Capability Structure implemented. Otherwise, NULL. Variable RO

[19:16]

Version. PCIe specification defined value for VSEC version. 1

RO

[15:0]

PCI Express Extended Capability ID. PCIe specification defined value for VSEC Capability ID. 0x000B

RO