L-Tile and H-Tile Avalon® Memory-mapped+ Intel® FPGA IP for PCI Express* User Guide

ID 683527
Date 9/13/2024
Public
Document Table of Contents

6.1.4.4. User Configurable Device and Board ID

Table 56.  User Configurable Device and Board ID - 0xB9C

Bits

Register Description

Default Value

Access

[15:0]

Allows you to specify ID of the .sof file to be loaded.

From configuration bits RO