AN 320: Using Intel® FPGA IP Evaluation Mode

ID 683502
Date 10/22/2018
Public

1.7. Using Intel® FPGA IP Evaluation Mode in Teams ( Intel® Quartus® Prime Standard Edition)

The Intel® Quartus® Prime Standard Edition software supports Intel® FPGA IP Evaluation Mode in a team with distributed design tasks. The Intel® FPGA IP Evaluation Mode allows individual designers to simulate and hardware test a design containing licensed IP, without requiring licenses for each designer. However, ultimately you must generate the production-ready FPGA programming file on a machine with an available full production license for all licensed Intel® FPGA IP cores in the design.

The most flexible methodology for distributed work flows is for every designer to have a production license for all Intel® FPGA IP included in their portion of the design. However, you can use the Intel® Quartus® Prime Standard Edition incremental compilation feature to temporarily avoid the licensing requirement by following these steps on any machine with an Intel® Quartus® Prime Standard Edition license:

  1. Click Assignments > Settings > Compilation Process Settings > More Settings, and disable OpenCore plus hardware evaluation.
    Note: You cannot use incremental compilation to compile a portion of your design that contains licensed Intel® FPGA IP in evaluation mode, and then import that design as a pre-compiled module to another machine that has a production license for the IP.
  2. To compile the design, click Processing > Start Compilation.
  3. To export the compilation results as a design partition, click Project > Export Design Partition. The Intel® Quartus® Prime software generates an Intel® Quartus® Prime Exported Partition File (.qxp) in the project directory.
  4. To generate a full production, non-time-limited device programming file for the exported partition, you must import the partition to a project with access to a full production license for all licensed Intel® FPGA IP cores in the design. Click Project > Import Design Partitions to import a design partition.

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