AN 320: Using Intel® FPGA IP Evaluation Mode

ID 683502
Date 10/22/2018
Public

1.3. Intel® FPGA IP Evaluation Mode Messages

The Intel® Quartus® Prime Compiler generates messages about IP cores under Intel® FPGA IP Evaluation Mode. During compilation, the Compiler reports the soonest, untethered expiration time for all licensed Intel® FPGA IP cores in the design. The Compiler also reports the tethered mode evaluation time if all licensed Intel® FPGA IP cores in the design support tethered mode.
Figure 4. IP Evaluation Time Limit Messages
Note: The precise time of IP core evaluation timeout depends on the target FPGA device family and operating conditions.

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