R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/04/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

E.1. Margin Masks Overview

The margin mask is provided in the following table for reference. These margin masks provide a risk assessment for the FPGA PCIe interfaces on Intel R-Tile Avalon Streaming designs.

Note: The margin mask table validation data is based on the Intel Eagle Stream platform with an internal validation board (at PCIe slot B) whose total insertional loss ranges from 33dB to 36dB (from lane0 to lane15). The margin mask provided is subject to change as the customer system design is not the same as the validation system.
Table 118.  Margin Mask Values for the R-Tile Avalon Streaming Intel FPGA IP for PCI Express
Link Speed Bit Error Rate Number of Parts x Number of Repetitions Time Margin (ps) Voltage Margin Up (mV) Voltage Margin Down (mV)
PCIe 3.0 1e-9 5x5 8.44 90.37 89.93
1e-12 5x5 9.94 91.83 93.22
PCIe 4.0 1e-9 5x5 5.52 47.09 47.15
1e-12 5x5 7.01 51.34 51.89
PCIe 5.0 1e-9 5x5 1.98 35.86 33.91
1e-12 5x5 2.65 41.8 39.35
Note: For the Time Margin (horizontal), the R-Tile Debug Toolkit only reports the minimum margin measured between the left margin and the right margin.