R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/04/2023

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6.1.2. Debugging Device Enumeration Issues

Device enumeration is performed at the system level for all the PCIe devices included in the system. The enumeration algorithm is in charge of performing the correct exploration of all the potential PCIe devices that may be included. You can refer to Root Port Enumeration for an example of how this algorithm can be implemented by a Root Port.

During enumeration, the majority of TLPs being transmitted at the link level are Configuration TLPs. In general, if the Link training was performed correctly, the R-Tile Avalon-ST IP responds to any Configuration TLP received. However, if link instability is present, some of these Configuration TLPs may not be received correctly and hence cause enumeration problems. Refer to the section Debugging Link Training Issues to ensure your link is operating correctly. In addition, you can use the Debug Toolkit event counters, described in Event Counters, to ensure Configuration TLPs are being transferred at the link level.