R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 12/04/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

1.4. Device Family Support

The following terms define device support levels for Intel® FPGA IP cores:

  • Advance support—the IP core is available for simulation and compilation for this device family. Timing models include initial engineering estimates of delays based on early post-layout information. The timing models are subject to change as silicon testing improves the correlation between the actual silicon and the timing models. You can use this IP core for system architecture and resource utilization studies, simulation, pinout, system latency assessments, basic timing assessments (pipeline budgeting), and I/O transfer strategy (data-path width, burst depth, I/O standards tradeoffs).
  • Preliminary support—the IP core is verified with preliminary timing models for this device family. The IP core meets all functional requirements, but might still be undergoing timing analysis for the device family. It can be used in production designs with caution.
  • Final support—the IP core is verified with final timing models for this device family. The IP core meets all functional and timing requirements for the device family and can be used in production designs.
Table 5.  Device Family Support

Device Family

Support Level

Intel Agilex® 7

Advance support

Other device families

No support

Refer to the Intel PCI Express Solutions web page on the Intel website for support information on other device families.

Note: In the Intel® Quartus® Prime latest release, the R-Tile Avalon Streaming Intel FPGA IP for PCI Express is only available in the Intel Agilex® 7 I-Series and M-Series devices.