R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/02/2023
Public

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4.3.1.2.4. RX Flow Control Interface

The RX flow control interface provides information on the application's available RX buffer space for Posted (P), Non-Posted (NP) and Completion (CPL) transactions to the PCIe Hard IP. It reports the space available in number of credits as specified by the PCIe Specification.

The Application logic must ensure that enough credits are provided to the R-Tile Avalon-ST IP for PCIe during the Credit Initialization phase. This is to prevent a performance impact caused by the lack of credits available between the IP and the Application logic. Depending on the number of P, NP and CPL transactions happening at the PCIe link level, a lack of credit scenario may happen if the number of credits advertised by the Application logic is less than the credits advertised by the R-Tile Avalon-ST IP for PCIe to the link partner.

Flow control credits are available for the following TLP categories:
  • Posted (P) transactions: TLPs that do not required a response.
  • Non-poseted (NP) transactions: TLPs that require a completion.
  • Completions (CPL): TLPs that respond to non-posted transactions.
Table 51.  Credits Advertised by the R-Tile Avalon-ST IP for PCIe to the Link PartnerNote: The credit unit in this table follows the PCIe Specification where 1 credit = 4 DWs = 16 Bytes.
Port Hard IP Mode Posted Headers Posted Data Non-Posted Headers Non-Posted Data Completion Headers Completion Data
Port 0 Endpoint 784 1456 784 392 0 (infinite) 0 (infinite)
Root Port 784 1456 784 392 0 (infinite) 0 (infinite)
Upstream Port 784 1456 784 392 1024 2816
Downstream Port 784 1456 784 392 1024 2816
Port 1 Endpoint 392 760 392 196 0 (infinite) 0 (infinite)
Root Port 392 760 392 196 0 (infinite) 0 (infinite)
Upstream Port 392 760 392 196 512 1408
Downstream Port 392 760 392 196 512 1408
Port 2 Endpoint 224 444 224 112 0 (infinite) 0 (infinite)
Root Port 224 444 224 112 0 (infinite) 0 (infinite)
Upstream Port 224 444 224 112 256 704
Downstream Port 224 444 224 112 256 704
Port 3 Endpoint 224 444 224 112 0 (infinite) 0 (infinite)
Root Port 224 444 224 112 0 (infinite) 0 (infinite)
Upstream Port 224 444 224 112 256 704
Downstream Port 224 444 224 112 256 704

For more information on how credit control in general is implemented in this IP, refer to Credit Control.

Note: In some systems, there are broadcast Message TLPs being sent by the link partner during the PCIe enumeration process. Failing to properly initialize and return the corresponding credits from the Application logic to the R-Tile Avalon® Streaming IP may cause enumeration issues due to the priority order between Message TLPs and the Completions required for Configuration TLPs. Application logic must ensure proper credits are returned to the R-Tile Avalon® Streaming IP for any TLP that it receives.
Table 52.  Categorization of Transaction Types
TLP Type Category
Memory Write Posted
Memory Read Non-Posted
Memory Read Lock
I/O Read
I/O Write
Configuration Read
Configuration Write
Fetch and Add AtomicOp
Message Posted
Completion Completion
Completion with Data
Completion Lock
Completion Lock with Data
Table 53.  RX Flow Control Interface Signals
Signal Name Direction Description EP/RP/BP Clock Domain
pX_rx_st_hcrdt_update_i[2:0] where

X = 0, 1, 2, 3 (IP core number)

Input

Indicates credit is made available for the different types of Header.

Each Header (including the TLP Prefix, if any) consumes one credit.

[0] : Posted Header (PH)

[1] : Non-Posted Header (NPH)

[2] : Completion Header (CPLH)

To advertise infinite credits for a specific TLP type between the IP and the Application logic, the corresponding bit within this signal bus must be asserted for one clock cycle, with a value of 0 on the corresponding bits for the targeted TLP type in the pX_rx_st_hcrdt_update_cnt_i signal bus during the credit initialization phase.

EP/RP/BP coreclkout_hip
pX_rx_st_hcrdt_update_cnt_i[5:0] where

X = 0, 1, 2, 3 (IP core number)

Input

Indicates number of credits released.

[1:0] : number of PH credits released

[3:2] : number of NPH credits released

[5:4] : number of CPLH credits released

Valid when the corresponding pX_rx_st_hcrdt_update_i bit = 1.

The maximum number of credits released is three.

To advertise infinite credits for a specific TLP type between the IP and the Application logic, the corresponding bits within this signal bus must be set to 0 during the credit initialization phase (when the corresponding pX_rx_st_hcrdt_update_i bit is asserted for one clock cycle).

EP/RP/BP coreclkout_hip
pX_rx_st_hcrdt_init_i[2:0] where

X = 0, 1, 2, 3 (IP core number)

Input

Credit Initialization indicator. These signals remain high for entire initialization phase. A High to Low transition indicates the completion of the credit initialization phase.

[0] : PH

[1] : NPH

[2] : CPLH

EP/RP/BP coreclkout_hip
pX_rx_st_hcrdt_init_ack_o[2:0] where

X = 0, 1, 2, 3 (IP core number)

Output

Indicates the Host is ready for the credit initialization phase

[0] : PH

[1] : NPH

[2] : CPLH

EP/RP/BP coreclkout_hip
pX_rx_st_dcrdt_update_i[2:0] where

X = 0, 1, 2, 3 (IP core number)

Input

Indicates credit is made available for the different types of Data.

[0] : Posted Data (PD)

[1] : Non-Posted Data (NPD)

[2] : Completion Data (CPLD)

To advertise infinite credits for a specific TLP type between the IP and the Application logic, the corresponding bit within this signal bus must be asserted for one clock cycle, with a value of 0 on the corresponding bits for the targeted TLP type in the pX_rx_st_dcrdt_update_cnt_i signal bus during the credit initialization phase.

EP/RP/BP coreclkout_hip
pX_rx_st_dcrdt_update_cnt_i[11:0] where

X = 0, 1, 2, 3 (IP core number)

Input

Indicates number of credits released.

[3:0] : number of PD credits released

[7:4] : number of NPD credits released

[11:8] : number of CPLD credits released

Valid when the corresponding pX_rx_st_dcrdt_update_i bit = 1.

The maximum number of credits released is 15.

To advertise infinite credits for a specific TLP type between the IP and the Application logic, the corresponding bits within this signal bus must be set to 0 during the credit initialization phase (when the corresponding pX_rx_st_dcrdt_update_i bit is asserted for one clock cycle).

Note: The initial RX NPD credits must be equal or larger than the Maximum Payload Size.
EP/RP/BP coreclkout_hip
pX_rx_st_dcrdt_init_i[2:0] where

X = 0, 1, 2, 3 (IP core number)

Input

Credit Initialization indicator. These signals remain high for entire initialization phase. A High to Low transition indicates the completion of the credit initialization phase.

[0] : PD

[1] : NPD

[2] : CPLD

EP/RP/BP coreclkout_hip
pX_rx_st_dcrdt_init_ack_o[2:0] where

X = 0, 1, 2, 3 (IP core number)

Input

Indicates the Host is ready for the credit initialization phase

[0] : PD

[1] : NPD

[2] : CPLD

EP/RP/BP coreclkout_hip