R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683501
Date 10/02/2023

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Document Table of Contents

E.1. Margin Masks Overview

The official margin mask is provided in the following table for reference. These margin masks provide a risk assessment for the FPGA PCIe interfaces on Intel R-Tile Avalon Streaming designs.

Table 118.  Margin Mask Values for the R-Tile Avalon Streaming Intel FPGA IP for PCI Express
Link Speed Bit Error Rate Number of Parts x Number of Repetitions Minimum Time Margin (ps) Minimum Voltage Margin Up (mV) Minimum Voltage Margin Down (mV)
PCIe 3.0 1e-9 5x5 8.44 90.37 89.93
1e-12 5x5 9.94 91.83 93.22
PCIe 4.0 1e-9 5x5 5.52 47.09 47.15
1e-12 5x5 7.01 51.34 51.89
PCIe 5.0 1e-9 5x5 1.98 35.86 33.91
1e-12 5x5 2.65 41.8 39.35
Note: For the Time Margin (horizontal), the R-Tile Debug Toolkit only reports the minor margin measured between the left margin and the right margin.