Avalon Verification IP Suite: User Guide

ID 683439
Date 8/28/2025
Public
Document Table of Contents

19.1.1. Running the Verilog HDL Testbench for a Single Avalon-MM Master and Slave Pair

  1. Unzip ug_avalon_verification.zip to a working directory.
  2. Create a new project.
    1. For the Quartus® Prime Standard Edition software, create this project in <working_dir>/avlmm_1x1_verilog.
    2. For the Quartus® Prime Pro Edition software, create this project in <working_dir>/avlmm_1x1_verilog_pro.
  3. Open avlm_avls_1x1.qsys in Platform Designer, and convert if needed.
  4. Complete the following steps to generate the testbench:
    1. On the Generate menu, select Generate HDL.
    2. Under Create simulation model, select Verilog.
    3. Click Generate.

      The Generate window displays informational messages as it generates the testbench.

    4. Close the Generate window.
  5. Start the QuestaSim* simulator.
  6. On the File menu, select Change Directory.
    1. For the Quartus® Prime Standard Edition software, change the directory to <working_dir>/avlmm_1x1_verilog/.
    2. For the Quartus® Prime Pro Edition software, change the directory to <working_dir>/avlmm_1x1_verilog_pro/.
  7. To run the simulation, type the following command in the transcript console:

    do run_simulation.tcl