Avalon Verification IP Suite: User Guide

ID 683439
Date 8/28/2025
Public
Document Table of Contents

19.1.2. Running the Verilog HDL Testbench for the Two Avalon-MM Masters and Slaves

  1. Unzip ug_avalon_verification.zip to a working directory.
  2. Create a new project.
    1. For the Quartus® Prime Standard Edition software, create this project in <working_dir>/avlmm_2x2_verilog.
    2. For the Quartus® Prime Pro Edition software, create this project in <working_dir>/avlmm_2x2_verilog_pro.
  3. Open avlm_avls_2x2.qsys in Platform Designer, and convert if needed.
  4. Complete the following steps to generate the testbench:
    • On the Generate menu, select Generate HDL.
    • Under Create simulation model, select Verilog.
    • Click Generate.

      The Generate window displays informational messages as it generates the testbench.

  5. Close the Generate window.
  6. Start the QuestaSim* simulator.
  7. On the File menu, select Change Directory.
    1. For the Quartus® Prime Standard Edition software, change the directory to <working_dir>/avlmm_2x2_verilog.
    2. For the Quartus® Prime Pro Edition software, change the directory to <working_dir>/avlmm_2x2_verilog_pro.
  8. To run the simulation, type the following command in the transcript console:
    do run_simulation.tcl