Avalon Verification IP Suite: User Guide

ID 683439
Date 8/28/2025
Public
Document Table of Contents

19.2.2. Running the Testbench for Two Avalon-MM Masters Slaves

  1. Unzip ug_avalon_verification.zip to a working directory.
  2. Create a new project.
    1. For the Quartus® Prime Standard Edition software, create this project in <working_dir>/avlmm_2x2_vhdl.
    2. For the Quartus® Prime Pro Edition software, create this project in <working_dir>/avlmm_2x2_vhdl_pro.
  3. Open avlm_avls_2x2.qsys in Platform Designer, and convert if needed.
  4. Complete the following steps to generate the testbench:
    • On the Generate menu, select Generate HDL.
    • Under Create simulation model, select VHDL.
    • Click Generate.

      The Generate window displays informational messages as it generates the testbench.

  5. Close the Generate window.
  6. If using the Quartus® Prime Pro Edition software, you may need to modify the suffix of the bfm library names throughout test_program.vhdl and test_program_pkg.vhdl as provided in the ./libraries folder.
    i.e.
    library altera_avalon_mm_master_bfm_191;
    library altera_avalon_mm_slave_bfm_191;
  7. Start the QuestaSim* simulator.
  8. On the File menu, select Change Directory.
    1. For the Quartus® Prime Standard Edition software, change the directory to <working_dir>/avlmm_2x2_vhdl.
    2. For the Quartus® Prime Pro Edition software, change the directory to <working_dir>/avlmm_2x2_vhdl_pro.
  9. To run the simulation, type the following command in the transcript console:
    do run_simulation.tcl

    This command compiles all the required HDL files, elaborates, and runs the simulation.