Avalon Verification IP Suite: User Guide

ID 683439
Date 8/28/2025
Public
Document Table of Contents

18.2.1. Creating the Platform Designer Design

In this section you generate a testbench system in Platform Designer for the DUT.

Before you run the design file, unzip the ug_avalon_verification.zip file to a working directory on your hard drive. This location is referred to as <working_directory> .

  1. Create a new Quartus® Prime project.
    1. For the Quartus® Prime Standard Edition software, create this project in the <working_directory>/avlst_verilog directory.
    2. For the Quartus® Prime Pro Edition software, create this project in the <working_directory>/avlst_verilog_pro directory.
  2. On the Tools menu, click Platform Designer .
  3. In Platform Designer, open st_bfm_qsys_tutorial.qsys. This design implements a single-clock FIFO, which will be the device under test.