10Gbps Ethernet Accelerator Functional Unit (AFU) Design Example User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683422
Date 4/30/2019
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Overview 3. Running the Design Example Tests 4. Using the Design Example as a Platform for Further Evaluation 5. 10Gbps Ethernet AFU Design Example User Guide Archives A. Document Revision History for 10Gbps Ethernet AFU Design Example User Guide
1. About this Document x
1.1. Intended Audience 1.2. Conventions 1.3. Acronym List 1.4. Acceleration Glossary
2. Overview x
2.1. 10GbE Design Example AFU Hardware 2.2. 10GbE Design Example AFU Software
3. Running the Design Example Tests x
3.1. Setup Prerequisites 3.2. Running 10GbE Internal Loopback Test in Single Intel® PAC System 3.3. Running 10GbE External Loopback Test in Single Intel® PAC System 3.4. Running 10GbE Intel® PAC-to-PAC Test between two connected Intel® PACs
4. Using the Design Example as a Platform for Further Evaluation x
4.1. Prerequisite while Evaluating with the Intel FPGA MAC IP 4.2. Evaluation with an Alternate MAC IP
1. About this Document
2. Overview
3. Running the Design Example Tests
4. Using the Design Example as a Platform for Further Evaluation
5. 10Gbps Ethernet AFU Design Example User Guide Archives
A. Document Revision History for 10Gbps Ethernet AFU Design Example User Guide

3.2. Running 10GbE Internal Loopback Test in Single Intel® PAC System

  1. Load the AF for the 10GbE AFU example. 
    $ cd $OPAE_PLATFORM_ROOT
$ sudo fpgaconf hw/samples/eth_e2e_e10/bin/eth_e2e_e10.gbs
  2. cd $OPAE_PLATFORM_ROOT/hw/samples/eth_e2e_e10/sw
  3. Run the following steps on your Intel® PAC:
    1. Compile the library and application using the command: 
      $ make
    2. To configure the transceiver channel into 10G mode, write 10 to the following sysfs entry: 
      $ sudo sh -c "echo 10 > /sys/class/fpga/intel-fpga-dev.<instance_id>\
/intel-fpga-fme.<instance_id>/intel-pac-hssi.<instance_id>.\
auto/hssi_mgmt/config"

      <instance_id> represents the consecutive numbering of device, fme, and hssi instances. 

      For example:
sudo sh -c "echo 10 > /sys/class/fpga/intel-fpga-dev.0\
/intel-fpga-fme.0/intel-pac-hssi.2.auto/hssi_mgmt/config"
    3. To allow non-root users to access the 10GbE AFU instance, you can provide read and write privileges to the port (/dev/intel-fpga-port.\*) where \* denotes the respective socket. For example, to provide read and write privileges on Port 0: 
      $ sudo chmod 666 /dev/intel-fpga-port.0
    4. To resolve library dependency: 
      export LD_LIBRARY_PATH=`pwd`:$LD_LIBRARY_PATH
    5. To enable the internal loopback on B:D:F - 00:0a:0b, 
      $ ./pac_hssi_e10 -b 00 -d 0a -f 0b --action=loopback_enable
    6. To clear PHY, transmit, and receive statistics: 
      $ ./pac_hssi_e10 -b 00 -d 0a -f 0b --channel=0 --action=stat_clear
      Sample output: 
      Cleared TX stats on channel 0
Cleared RX stats on channel 0
    7. To transmit 0x1000 packets: 
      $ ./pac_hssi_e10 -b 00 -d 0a -f 0b --channel=0 --action=pkt_send
      Sample output: 
      Sent 0x10000 packets on channel 0
      Note: After programming the eth_e2e_e10 AFU, the initial send of packets may drop the first packet. Subsequent packet sends do not drop any packets.
    8. To get PHY, transmit and receive statistics: 
      $ ./pac_hssi_e10 -b 00 -d 0a -f 0b --channel=0 --action=stat
    To find the instance id associated with your device: 
    $ ls /sys/class/fpga/
    For more details, refer to the README file located in the sw subdirectory to: 
    $OPAE_PLATFORM_ROOT/hw/samples/eth_e2e_e10/sw/README.md

    To run this example on a virtual machine:

    1. Program the eth_e2e_e10 AFU and configure the transceiver channel to 10G mode from the Host machine by referencing the previous substeps.
    2. Follow the steps in the Running the OPAE in a Virtualized Environment section of the Intel® Acceleration Stack Quick Start Guide for Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA to create a virtual function and attach the virtual function to a virtual machine.
    3. Run the internal loopback test on the virtual machine.
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