1.3. Acronym List
|AFU||Accelerator Functional Unit||Hardware Accelerator implemented in FPGA logic, which offloads a computational operation for an application from the CPU to improve performance.|
|AF||Accelerator Function||Compiled Hardware Accelerator image implemented in FPGA logic that accelerates an application. An AFU and associated AFs are also referred as GBS (Green-Bits, Green BitStream) in the Acceleration Stack installation directory tree and in source code comments.|
|API||Application Programming Interface||A set of subroutine definitions, protocols, and tools for building software applications.|
|ASE||AFU Simulation Environment||Co-simulation environment that allows you to use the same host application and AF in a simulation environment. ASE is part of the Intel Acceleration Stack for FPGAs.|
|CCI-P||Core Cache Interface||CCI-P is the standard interface that AFUs use to communicate with the host.|
|FIU||FPGA Interface Unit||FIU is a platform interface layer that acts as a bridge between platform interfaces like PCIe* , UPI, and AFU-side interfaces such as CCI-P.|
|FIM||FPGA Interface Manager||The FPGA hardware containing the FPGA Interface Unit (FIU) and external interfaces such as interfaces for memory, and networking.
The FIM is also referred as BBS (Blue-Bits, Blue BitStream) in the Acceleration Stack installation directory tree and in source code comments.
The AF interfaces with the FIM at run time.
|NLB||Native Loopback||The NLB performs reads and writes to the CCI-P link to test connectivity and throughput.|
|OPAE||Open Programmable Acceleration Engine||The OPAE is a software framework for managing and accessing AFs.|
|HSSI||High Speed Serial Interface||This is a reference to the multi-gigabit serial transceiver I/O in the FIM and the corresponding interface to the AFU.|
|PR||Partial Reconfiguration||The ability to dynamically reconfigure a portion of an FPGA while the remaining FPGA design continues to function.|
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