10Gbps Ethernet Accelerator Functional Unit (AFU) Design Example User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

Download
ID 683422
Date 4/30/2019
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. Overview 3. Running the Design Example Tests 4. Using the Design Example as a Platform for Further Evaluation 5. 10Gbps Ethernet AFU Design Example User Guide Archives A. Document Revision History for 10Gbps Ethernet AFU Design Example User Guide
1. About this Document x
1.1. Intended Audience 1.2. Conventions 1.3. Acronym List 1.4. Acceleration Glossary
2. Overview x
2.1. 10GbE Design Example AFU Hardware 2.2. 10GbE Design Example AFU Software
3. Running the Design Example Tests x
3.1. Setup Prerequisites 3.2. Running 10GbE Internal Loopback Test in Single Intel® PAC System 3.3. Running 10GbE External Loopback Test in Single Intel® PAC System 3.4. Running 10GbE Intel® PAC-to-PAC Test between two connected Intel® PACs
4. Using the Design Example as a Platform for Further Evaluation x
4.1. Prerequisite while Evaluating with the Intel FPGA MAC IP 4.2. Evaluation with an Alternate MAC IP
1. About this Document
2. Overview
3. Running the Design Example Tests
4. Using the Design Example as a Platform for Further Evaluation
5. 10Gbps Ethernet AFU Design Example User Guide Archives
A. Document Revision History for 10Gbps Ethernet AFU Design Example User Guide

2. Overview

The 10Gbps Ethernet (10GbE) AFU design example in the Acceleration Stack installation allows you to evaluate the network port capabilities of the Intel® PAC with Intel® Arria® 10 GX FPGA. The 10GbE AFU design example contains four instances of 10GbE MAC, each with its own traffic generation and checking logic to send and receive ethernet packets on the QSFP+ network port. The Acceleration Stack installation includes OPAE tools, APIs and a sample host application to initialize and start packet transfers from the host, and subsequently retrieve port statistics.

This design example supports internal HSSI transceiver loopback, external QSFP+ port loopback, and Intel® PAC-to-PAC modes of operation.
Figure 1. System Block Diagram
Level Two Title

Did you find the information on this page useful?

Characters remaining:

Feedback Message