Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Release Notes

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ID 683415
Date 4/11/2018
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Document Table of Contents
Document Table of Contents x
Notice Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Release Notes
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Release Notes x
Acceleration Acronym List System Requirements Intel® Acceleration Stack 1.0 Reference Table Enhancements Known Issues Issues Resolved Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Release Notes Revision History
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Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Release Notes

Issues Resolved

Table 5.  Issues Resolved in the Intel Acceleration Stack Version 1.0
Area Description
fpgabist Tool and DMA Bandwidth numbers reported by dma_test are now accurate.
FPGA Interface Manager (FIM) When using the automatic virtual channel (VA), all AFU traffic now routes to VH0 (PCIe). The routing assignment was undefined in the Acceleration Stack 1.0 Beta release.
Open Programmable Acceleration Engine (OPAE) OpenCL* host applications now handle all kernel interrupts. In the Acceleration Stack 1.0 Beta version, the host application may hang due to missing kernel interrupts.
Accelerator Functional Unit (AFU) run.sh no longer requires two SR-IOV licenses when using a floating license. The Acceleration Stack 1.0 Beta version requests two licenses in this case.
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