|A different OPN is used in the design examples.||The Intel® Quartus® Prime Pro Edition license uses a design example OPN of 10AX115N3F40E2SG, instead of the Intel® PAC with Intel® Arria® 10 GX FPGA OPN of 10AX115N2F40E2LG. This difference does not impact your design. The design example OPN variance will be corrected to match the platform OPN in the Intel® Acceleration Stack 1.1 version.|
|PCIe directed speed changes are not supported.||Only automatic down-training at boot time is supported.|
|Virtual Function (VF) may fail to attach or detach when using the Linux* Red Hat* 3.10 kernel. This is a known issue with qemu/kvm and libvirt.||Refer to the Red Hat* website for more information about this issue.|
|The Intel® FPGA Dynamic Profiler Tool for OpenCL* GUI reports frequency and bandwidth incorrectly.||This issue will be resolved in a future version of Intel® Acceleration Stack.|
|fpgainfo may raise a UnicodeEncodeError when the Python* interpreter cannot determine what encoding to use. This issue typically occurs when redirecting or piping output. The fpgabist tool calls fpgainfo and is also impacted.||There are two workarounds for this issue:
|When simulating the hello_intr_afu sample code, the af2cp_sTxPort.c1.hdr.rsvd2[5:4] has a value of X.||This issue will be resolved in the Intel® Acceleration Stack 1.1 version.|
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