Interlaken (2nd Generation) Intel® FPGA IP User Guide

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ID 683396
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. Register Map 7. Test Features 8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives 9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide
1. Introduction x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Flexible Lanes Support 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA 2.6. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignment 2.6.2. Adding the External PLL 2.6.3. PMA Adaptation Flow
3. Parameter Settings x
3.1. Main Parameters 3.2. PMA Adaptation Parameters
4. Functional Description x
4.1. Interfaces 4.2. IP Clocks 4.3. High Level Data Path Flow for Interlaken Mode 4.4. High Level Data Path Flow for Interlaken Look-aside Mode 4.5. Modes of Operation 4.6. Performance 4.7. IP Core Reset 4.8. M20K ECC Support 4.9. Out-of-Band Flow Control
4.3. High Level Data Path Flow for Interlaken Mode x
4.3.1. Interlaken TX Path 4.3.2. Interlaken RX Path 4.3.3. Unused Transceiver Channels
4.3.1. Interlaken TX Path x
4.3.1.1. Transmit Path Blocks 4.3.1.2. In-Band Calendar Bits on Transmit Side
4.3.2. Interlaken RX Path x
4.3.2.1. Receive Path Blocks 4.3.2.2. In-Band Calendar Bits on Receive Side 4.3.2.3. RX Errored Packet Handling
4.3.2.3. RX Errored Packet Handling x
4.3.2.3.1. Example With Errors and In-Band Calendar Bits
4.4. High Level Data Path Flow for Interlaken Look-aside Mode x
4.4.1. Interlaken Look-aside TX Path 4.4.2. Interlaken Look-aside RX Path
4.4.1. Interlaken Look-aside TX Path x
4.4.1.1. Transmit Path Blocks
4.4.2. Interlaken Look-aside RX Path x
4.4.2.1. Receive Path Blocks 4.4.2.2. RX Error Handling
4.5. Modes of Operation x
4.5.1. Interleaved and Packet Modes 4.5.2. Interlaken Mode 4.5.3. Interlaken Look-aside Mode 4.5.4. Multi-Segment Mode
4.5.2. Interlaken Mode x
4.5.2.1. Transmit User Data Interface Examples 4.5.2.2. Receive User Data Interface Example
4.5.3. Interlaken Look-aside Mode x
4.5.3.1. Transmit User Data Interface Example 4.5.3.2. Receive User Data Interface Example
4.5.4. Multi-Segment Mode x
4.5.4.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals 5.7. External PLL Interface Signals
7. Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode
1. Introduction
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. Register Map
7. Test Features
8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives
9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide

4.2. IP Clocks

Table 21.  Interlaken IP Core Clocks

Clock Name

Device

Direction

Description

pll_ref_clk
  • Intel® Stratix® 10 L-, H-, and E-tile
  • Intel® Agilex™ 7 E-tile
Input

Reference clock for the RX CDR PLL.

tx_serial_clk[NUM_LANES–1:0] Intel® Stratix® 10 L- and H-Tile Input

Clocks for the individual transceiver channels in Interlaken IP.

rx_usr_clk
  • Intel® Stratix® 10 L-, H-, and E-tile
  • Intel® Agilex™ 7 E-tile
Input
Clock for the receive application interface.
Note: This clock is not present in Interlaken Look-aside IP core variations.
tx_usr_clk
  • Intel® Stratix® 10 L-, H-, and E-tile
  • Intel® Agilex™ 7 E-tile
Input

Clock for the transmit application interface.

Note: This clock is not present in Interlaken Look-aside IP core variations.
reconfig_clk
  • Intel® Stratix® 10 L-, H-, and E-tile
  • Intel® Agilex™ 7 E-tile
Input

Management clock for hard PCS register access, including access for transceiver reconfiguration and testing features. Refer to the appropriate Transceiver PHY User Guide for the frequency of the reconfig_clk.

mm_clk
  • Intel® Stratix® 10 L-, H-, and E-tile
  • Intel® Agilex™ 7 E-tile
Input

Management clock for Interlaken IP core register access. Intel® recommends that you use the mm_clk value same as the reconfig_clk.

clk_tx_common
  • Intel® Stratix® 10 L-, H-, and E-tile
  • Intel® Agilex™ 7 E-tile
Output Transmit PCS common lane clock driven by the SERDES transmit PLL.
clk_rx_common
  • Intel® Stratix® 10 L-, H-, and E-tile
  • Intel® Agilex™ 7 E-tile
Output Receive PCS common lane clock driven by the CDR in transceiver.
mac_clkin Intel® Stratix® 10 and Intel® Agilex™ 7 E-Tile (PAM4 only) Input

This signal must be driven by a PLL. This PLL must use the same clock source that drives the pll_ref_clk .

The value of mac_clkin signal is 396 MHz.

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