Interlaken (2nd Generation) Intel® FPGA IP User Guide

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ID 683396
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. Register Map 7. Test Features 8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives 9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide
1. Introduction x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Flexible Lanes Support 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA 2.6. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignment 2.6.2. Adding the External PLL 2.6.3. PMA Adaptation Flow
3. Parameter Settings x
3.1. Main Parameters 3.2. PMA Adaptation Parameters
4. Functional Description x
4.1. Interfaces 4.2. IP Clocks 4.3. High Level Data Path Flow for Interlaken Mode 4.4. High Level Data Path Flow for Interlaken Look-aside Mode 4.5. Modes of Operation 4.6. Performance 4.7. IP Core Reset 4.8. M20K ECC Support 4.9. Out-of-Band Flow Control
4.3. High Level Data Path Flow for Interlaken Mode x
4.3.1. Interlaken TX Path 4.3.2. Interlaken RX Path 4.3.3. Unused Transceiver Channels
4.3.1. Interlaken TX Path x
4.3.1.1. Transmit Path Blocks 4.3.1.2. In-Band Calendar Bits on Transmit Side
4.3.2. Interlaken RX Path x
4.3.2.1. Receive Path Blocks 4.3.2.2. In-Band Calendar Bits on Receive Side 4.3.2.3. RX Errored Packet Handling
4.3.2.3. RX Errored Packet Handling x
4.3.2.3.1. Example With Errors and In-Band Calendar Bits
4.4. High Level Data Path Flow for Interlaken Look-aside Mode x
4.4.1. Interlaken Look-aside TX Path 4.4.2. Interlaken Look-aside RX Path
4.4.1. Interlaken Look-aside TX Path x
4.4.1.1. Transmit Path Blocks
4.4.2. Interlaken Look-aside RX Path x
4.4.2.1. Receive Path Blocks 4.4.2.2. RX Error Handling
4.5. Modes of Operation x
4.5.1. Interleaved and Packet Modes 4.5.2. Interlaken Mode 4.5.3. Interlaken Look-aside Mode 4.5.4. Multi-Segment Mode
4.5.2. Interlaken Mode x
4.5.2.1. Transmit User Data Interface Examples 4.5.2.2. Receive User Data Interface Example
4.5.3. Interlaken Look-aside Mode x
4.5.3.1. Transmit User Data Interface Example 4.5.3.2. Receive User Data Interface Example
4.5.4. Multi-Segment Mode x
4.5.4.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals 5.7. External PLL Interface Signals
7. Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode
1. Introduction
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. Register Map
7. Test Features
8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives
9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide

6. Register Map

The Interlaken IP core control registers are 32 bits wide and are accessible to you using the management interface, an Avalon-MM interface which conforms to the Avalon Interface Specifications. This table lists the registers available in the IP core. All unlisted locations are reserved.
Table 39.  IP Core Register Map

Offset

Name

R/W

Description

16'h0

PCS_BASE

RO

[31:8] – Constant “HSj” ASCII

[7:0] – version number

Despite its name, this register does not encode the hard PCS base address.

16'h1

LANE_COUNT

RO

Number of lanes

16'h3

ELAPSED_SEC

RO

[23:0] - Elapsed seconds since power up. The IP core calculates this value from the management interface clock (mm_clk) for diagnostic purposes. During continuous operation, this value rolls over every 194 days.

16'h4

TX_EMPTY

RO

[NUM_LANES–1:0] – Transmit FIFO status (empty)

16'h5

TX_FULL

RO

[NUM_LANES–1:0] – Transmit FIFO status (full)

16'h6

TX_PEMPTY

RO

[NUM_LANES–1:0] – Transmit FIFO status (partially empty)

16'h7

TX_PFULL

RO

[NUM_LANES–1:0] – Transmit FIFO status (partially full)

16'h8

RX_EMPTY

RO

[NUM_LANES–1:0] – Receive FIFO status (empty)

16'h9

RX_FULL

RO

[NUM_LANES–1:0] – Receive FIFO status (full)

16'hA

RX_PEMPTY

RO

[NUM_LANES–1:0] – Receive FIFO status (partially empty)

16'hB

RX_PFULL

RO

[NUM_LANES–1:0] – Receive FIFO status (partially full)
16'hC MAC_CLK_KHZ RO MAC clock frequency (kHz). This register is only available in E-tile PAM4 mode variations.

16'hD

RX_KHZ

RO

RX recovered clock frequency (kHz)
Note: This register assumes mm_clk frequency of 100 MHz, and scales accordingly if the mm_clk is not equal to 100 MHz.

16'hE

TX_KHZ

RO

TX serial clock frequency (kHz)

16'h10

PLL_LOCKED

RO

In L-tile and H-tile device variations:
  • Bit[0] – Transmit PLL lock indication. One lock indicator per transceiver block. Bits that correspond to unused transceiver block PLLs are forced to 1.
In E-tile device variations:
  • Bit[16] – MAC clock PLL lock indication.
  • Bit[0] – Transmit PLL lock indication. One lock bit for all transceivers.

16'h11

FREQ_LOCKED

RO

[NUM_LANES–1:0] – Clock data recovery is frequency locked on the inbound data stream

16'h12

LOOPBACK

RW

In Intel® Stratix® 10 L-tile and H-tile device variations:

[NUM_LANES–1:0] – For each lane, write a 1 to activate internal TX to RX serial loopback mode, or write a 0 to disable the loopback for normal operation.

In E-tile device variations:

Interlaken Intel FPGA IP core does not support this function. To enable internal serial loopback, perform Avalon® -MM read/write to E-tile registers. For more information refer to the Register Map section of the E-Tile Transceiver PHY User Guide.

16'h13

RESET

RW

Bit 9 : 1 = Force lock to data mode (Only in Intel® Stratix® 10 L- and H-tile device variations)

Bit 8 : 1 =Force lock to reference mode (Only in Intel® Stratix® 10 L- and H- tile device variations)

Bit 7 : 1 = Synchronously clear the TX-side error counters and sticky flags

Bit 6 : 1 = Synchronously clear the RX-side error counters and sticky flags

The normal operating state for this register is all zeros, to allow automatic reset control. These bits are intended primarily for hardware debugging use. Bits 6 and 7 are convenient for monitoring long stretches of error-free operation.

16'h20

ALIGN

RO

Bit 12 : RSFEC AM sync align (Only available in Intel® Stratix® 10 E-tile PAM4 mode device variations, not valid in NRZ mode)

Bit 0 : TX lanes are aligned

Bit 1 : RX lanes are aligned.

16'h21

WORD_LOCK

RO

[NUM_LANES–1:0] – Word (block) boundaries have been identified in the RX stream.

16'h22

SYNC_LOCK

RO

[NUM_LANES–1:0] – Metaframe synchronization has been achieved.

16'h23

CRC0

RO

4 bit counters indicating CRC errors in lanes [7:0].

These saturates at F, and you clear them by setting bit 6 in the RESET register.

16'h24

CRC1

RO

4 bit counters indicating CRC errors in lanes [15:8].

These saturates at F, and you clear them by setting bit 6 in the RESET register.

16'h25

CRC2

RO

4 bit counters indicating CRC errors in lanes [23:16].

These saturates at F, and you clear them by setting bit 6 in the RESET register.

16'h26

CRC3

RO

4 bit counters indicating CRC errors in lanes [31:24].

These saturates at F, and you clear them by setting bit 6 in the RESET register.

16'h28

RX_LOA

RO

Bit [0] – Sticky flag indicating loss of RX side lane-to-lane alignment since this bit was last cleared through the RESET register. Typically, the IP core asserts this bit in case of a catastrophic problem such as one or more lanes going down.

16'h29

TX_LOA

RO

Bit [0] – Sticky flag indicating loss of TX side lane to lane alignment since this bit was last cleared through the RESET register. Typically, the IP core asserts this bit in case of a TX FIFO underflow / overflow caused by a significant deviation from the expected data flow rate through the TX PCS.

16'h38

CRC32_ERR_INJECT

RW

[NUM_LANES–1:0] - When a bit has the value of 1, the IP core injects CRC32 errors on the corresponding TX lane. When it has the value of 0, the IP core does not inject errors on the TX lane. You must maintain each bit at the value of 1 for the duration of a meta Frame, at least, to ensure that the IP core transmits at least one CRC32 error.

16'h80 ILKN_FEC_XCODER_TX_ILLEGAL_STATE RO This register is only available in E-tile PAM4 mode variations. Transcoder detects illegal framing bits [66:64] of the Interlaken frame layer words. This is sticky bit.
16'h81 ILKN_FEC_XCODER_RX_UNCOR_FECCW RO This register is only available in E-tile PAM4 mode variations. FEC indicates uncorrectable FEC code word error. This register saturates at 4'b1111 for each lane.
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