Interlaken (2nd Generation) Intel® FPGA IP User Guide

Download PDF
ID 683396
Date 12/04/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. Register Map 7. Test Features 8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives 9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide
1. Introduction x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Flexible Lanes Support 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA 2.6. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignment 2.6.2. Adding the External PLL 2.6.3. PMA Adaptation Flow
3. Parameter Settings x
3.1. Main Parameters 3.2. PMA Adaptation Parameters
4. Functional Description x
4.1. Interfaces 4.2. IP Clocks 4.3. High Level Data Path Flow for Interlaken Mode 4.4. High Level Data Path Flow for Interlaken Look-aside Mode 4.5. Modes of Operation 4.6. Performance 4.7. IP Core Reset 4.8. M20K ECC Support 4.9. Out-of-Band Flow Control
4.3. High Level Data Path Flow for Interlaken Mode x
4.3.1. Interlaken TX Path 4.3.2. Interlaken RX Path 4.3.3. Unused Transceiver Channels
4.3.1. Interlaken TX Path x
4.3.1.1. Transmit Path Blocks 4.3.1.2. In-Band Calendar Bits on Transmit Side
4.3.2. Interlaken RX Path x
4.3.2.1. Receive Path Blocks 4.3.2.2. In-Band Calendar Bits on Receive Side 4.3.2.3. RX Errored Packet Handling
4.3.2.3. RX Errored Packet Handling x
4.3.2.3.1. Example With Errors and In-Band Calendar Bits
4.4. High Level Data Path Flow for Interlaken Look-aside Mode x
4.4.1. Interlaken Look-aside TX Path 4.4.2. Interlaken Look-aside RX Path
4.4.1. Interlaken Look-aside TX Path x
4.4.1.1. Transmit Path Blocks
4.4.2. Interlaken Look-aside RX Path x
4.4.2.1. Receive Path Blocks 4.4.2.2. RX Error Handling
4.5. Modes of Operation x
4.5.1. Interleaved and Packet Modes 4.5.2. Interlaken Mode 4.5.3. Interlaken Look-aside Mode 4.5.4. Multi-Segment Mode
4.5.2. Interlaken Mode x
4.5.2.1. Transmit User Data Interface Examples 4.5.2.2. Receive User Data Interface Example
4.5.3. Interlaken Look-aside Mode x
4.5.3.1. Transmit User Data Interface Example 4.5.3.2. Receive User Data Interface Example
4.5.4. Multi-Segment Mode x
4.5.4.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals 5.7. External PLL Interface Signals
7. Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode
1. Introduction
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. Register Map
7. Test Features
8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives
9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide

9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.12.04 23.4 21.1.3
  • The following IP sub-components have updates:
    • FIFO

    • E-tile Transceiver PHY

  • Added support for Questa*-Intel® FPGA Edition simulator.
2023.08.04 23.2 21.1.1 Updated the ordering code in the Interlaken (2nd Generation) Intel FPGA IP Core Release Information table.
2023.06.26 23.2 21.1.1
  • Updated the Round-trip Latency and Performance and Resource Utilization numbers.
  • Added VHDL support for synthesis and simulation model.
  • Added the mm_waitrequest signal to the IP Core Interface Signals figure and the Management Interface Signals table.
  • Updated the product family name to "Intel Agilex 7".
2022.09.26 22.1 20.0.3 Corrected the description of PCS_BASE register.
2022.04.04 22.1 20.0.3
  • Removed support for ModelSim* SE simulator.
  • Updated the Round-trip Latency and Performance and Resource Utilization numbers.
2021.10.04 21.3 20.0.1
  • Added support for QuestaSim* simulator.
  • Removed support for NCSim simulator.
2021.02.24 20.4 20.0.1
  • Added the following parameters:
    • Preserve unused transceiver channels for PAM4
    • Reference clock frequency for preserved channels
  • Added the pll_ref_clk[1] signal description in section: Clock and Reset Interface Signals.
  • Clarified the information about TX skew in section: Transmit Path Blocks.
2020.10.16 20.3 20.0.0
  • Changed the data rates support from 25.3 Gbps to 25.28 Gbps and 25.8 Gbps to 25.78 Gbps.
  • The IP now supports new data rate 25.78125 Gbps.
  • Updated Table: IP Supported Combinations of Number of Lanes and Data Rates to clarify the supported data rate/number of lanes combination for Interlaken look-aside IP variations.
  • Updated the data rate support information in the following sections:
    • Features
    • Flexible Lanes Support
    • Round-trip Latency
    • Parameter Settings
  • Updated Table: IP Theoretical Raw Aggregate Bandwidth for 25.28, 25.78, and 25.78125 Gbps data rates.
  • Updated Performance and Resource Utilization section for Intel® Quartus® Prime software version 20.3.
  • Added transceiver reference clock frequency for the 25.78125 Gbps data rate in the following sections:
    • Main Parameters
    • Clock and Reset Interface Signals
  • Updated section Release Information.
  • Updated Figure: IP Parameter Editor.
  • Clarified that Number of Segments parameter is grayed out for Interlaken Look-aside IP variations in Table: User Data Interface.
  • Updated the description of the reconfig_address signal for the E-tile PAM4 mode IP variations in Table: Reconfiguration Interface Signals.
2020.06.22 20.2 19.3.0
  • The IP now supports Interlaken Look-aside feature.
  • Updated the following section to include Interlaken Look-aside information:
    • Figure: Typical Interlaken Application
    • Features
    • Performance and Resource Utilization
    • Figure: IP Parameter Editor
    • Figure: Interlaken (2nd Generation) Intel FPGA IP High Level System Overview
  • The IP now supports 10x12.5 Gbps combination in H- and E-tile IP core variations.
  • Clarified the user clock frequency values for H- and E-tile device variations in Table: Recommended User Clock Frequency.
  • Added new parameter Enable Interlaken Look-aside mode in chapter: Parameter Settings.
  • Updated values of pll_ref_clk frequencies for H- and E-tile device variations in chapter: Parameter Settings.
  • Added new section PMA Adaptation Flow.
  • Added following new sections:
    • High Level Data Path Flow for Interlaken Look-aside Mode
    • Interlaken Look-aside Mode
  • Clarified that the design example provides logic to include out-of-band flow control functionality.
  • Modified Figure: IP Core Interface Signals to include new signals related to Interlaken Look-aside.
  • Added new signals related to Interlaken Look-aside in Chapter: Interface Signals and differentiate availability of the signals in two different modes of the IP.
  • Added new table Section: Clock and Reset Interface Signals to include frequency values for clk_tx_common.
  • Removed itx_hungry signal.
  • Removed Table: Transceiver Interface Signals.
2019.09.27 19.3 19.2.1
  • Added public support for Intel Agilex E-tile variants.
  • Updated Performance and Resource Utilization for L-, H-, and E-tile device variations.
  • Added topic Round trip Latency.
  • Renamed and updated the Figure: Interlaken (2nd Generation) Intel FPGA IP High-Level System Overview.
2019.07.01 19.2 19.2 Made the following changes:
  • Added EAP support for Intel Agilex E-tile variants.
  • Added information about the PMA Adaptation parameters available for the E-tile transceiver.
  • Added topic on preserving performance in unused E-tile transceivers.
  • Updated Performance and Resource Utilization for E-tile transceivers.
  • Added definitions of tx_pin_n and rx_pin_n signals. The PAM4 loopback example design uses these signals.
  • Added Interlaken Clock Domains figure to IP Core Clocks topic.
2018.12.24 18.1.1 18.1.1
  • Updated section Features.
  • Added the new supported combinations of number of lanes and data rates in Table: IP Core Supported Combinations of Number of Lanes and Data Rate.
  • Added new section Flexible Lanes Support.
  • Added new parameter Number of Segment in Table: Interlaken IP Core Parameter Settings: IP Tab.
  • Added new section Multi-Segment Mode.
  • Updated section Transmit User Interface Signals and Receive User Interface Signals.
  • Added the following new signals in Table: Transmit User Interface Signals:
    • itx_eob1
    • itx_eopbits1
    • itx_chan1
  • Added the following new signals in Table: Receive User Interface Signals:
    • irx_eob1
    • irx_eopbits1
    • irx_chan1
    • irx_err1
    • irx_err
  • Added new signal mac_pll_locked in Table: ATX PLL Interface Signals.
2018.09.24 18.1 18.1
  • Renamed the document title as Interlaken (2nd Generation) Intel Stratix 10 FPGA IP User Guide
  • Added VHDL simulation model and testbench support for Interlaken (2nd Generation) IP core.
  • Added information about additional clock mac_clkin for E-tile PAM4 mode variations in Adding the External PLL section and updated the description about this signal in Table: Interlaken IP Core Clocks.
  • Added new Interlaken IP core block diagrams for E-tile PAM4 mode in High Level System Flow section.
  • Made the following changes in Transmit Path Blocks section:
    • Added Figure: Interlaken IP Core Transmit Path Blocks for E-tile PAM4 Mode Device Variations
    • Updated information in TX MAC, TX PCS, and TX PMA sections for E-tile device variations.
  • Made the following changes in Receive Path Blocks section:
    • Added Figure: Interlaken IP Core Transmit Path Blocks for E-tile PAM4 Mode Device Variations
    • Updated information in RX MAC, RX PCS, and RX PMA sections for E-tile device variations.
  • Added new section Performance to showcase how to calculate bandwidth performance.
  • Updated signal description in Transmit User Interface Signals and Receive User Interface Signals.
  • Clarified the AVMM interface signals are available for the H-, L- and E-tile device variations.
  • Added steps to turn on internal serial loopback mode in IP core variations that target an E-tile devices.
  • Added following new registers related to E-tile device variations in Register Map section:
    • TX_READY_XCVR
    • RX_READY_XCVR
    • ILKN_FEC_XCODER_TX_ILLEGAL_STATE
    • ILKN_FEC_XCODER_RX_ILLEGAL_STATE
2018.07.16 18.0.1 18.0.1
  • Added support for the devices with E-tile transceivers.
  • Added 53.125 Gbps data rate support for Intel® Stratix® 10 E-tile devices in PAM4 mode.
  • Added the new supported combinations of number of lanes and data rates in Table: IP Core Supported Combinations of Number of Lanes and Data Rate.
  • Updated the Table: Performance and Resource Utilization for E-tile devices in NRZ and PAM4 mode.
  • Added new parameter XCVR Mode in Table: Interlaken IP Core Parameter Settings: IP Tab.
  • Added new Transceiver reference clock frequency values for 25.3, 25.8, and 26.5625 Gbps data rate in the Table: Interlaken IP Core Parameter Settings: IP Tab and Table: Clock and Reset Interface Signals.
  • Added clock signal mac_clkin in Table: Interlaken IP Core Clocks for Intel® Stratix® 10 E-tile PAM4 devices.
  • Updated Table: IP Core Register Map for E-tile devices.
2018.05.07 18.0 18.0
  • Renamed the document as Interlaken (2nd Generation) Intel FPGA IP User Guide
  • Added new 25.8 Gbps data rate support for number of lanes 6 and 12.
  • Added Cadence Xcelium Parallel simulator support.
  • Added new section Integrating Your IP Core in Your Design explaining how to make appropriate pin assignments and add external PLL.
  • Added the Transceiver reference clock frequency for 25.8 Gbps data rate in the Table: Interlaken IP Core Parameter Settings: IP Tab and Table: Clock and Reset Interface Signals.
  • Modified default setting value for the Tx Scrambler Seed parameter in Table: Interlaken IP Core Parameter Settings: IP Tab
  • Clarified the direction of the IP core clocks in Table: Interlaken IP Core Clocks.
Date Version Changes
November 2017 2017.11.06
  • Updated for Intel® Quartus® Prime Pro Edition 17.1 release.
  • Updated support for the Intel® Stratix® 10 devices with L-Tile and H-Tile transceivers in Table: IP Core Supported Combinations of Number of Lanes and Data Rate.
  • Added the resource utilization numbers for 25.3 Gbps data rate in Table: FPGA Resource Utilization.
  • Added support for Cadence NCSim simulator.
  • Added new parameter Transceiver Tile in Table: Interlaken IP Core Parameter Settings: IP Tab.
  • Removed 412.5 MHz pll_ref_clk frequency support for 25.3 Gbps data rate in Table: Clock and Reset Interface Signals.
  • Added new signal nad_cntr_inc in Table: Real-Time Receiver Status Signals.
Added the resource utilization numbers for 25.3May 2017 2017.05.08
  • Updated the resource utilization in Table: FPGA Resource Utilization.
  • Added the new supported combinations of number of lanes and data rate (6x25.3G and 12x25.3G) in Table: IP Core Supported Combinations of Number of Lanes and Data Rate
  • Corrected the steps for Specifying the IP Core Parameters and Options.
  • Added the transceiver reference clock frequency for 25.3 Gbps data rate in the Table: Interlaken IP Core Parameter Settings and Table: Clock and Reset Interface Signals.
December 2016 2016.12.19
  • Dynamic reconfiguration support is now available for Intel® Stratix® 10 devices.
  • Added a new parameter VCCR_GXB and VCCT_GXB supply voltage for the transceivers in the table: Interlaken IP Core Parameter Settings.
August 2016 2016.08.08 Initial version for Quartus Prime Pro – Stratix 10 Edition Beta software.
Level Two Title