Interlaken (2nd Generation) Intel® FPGA IP User Guide

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ID 683396
Date 8/04/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. Register Map 7. Test Features 8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives 9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide
1. Introduction x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Flexible Lanes Support 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA 2.6. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignment 2.6.2. Adding the External PLL 2.6.3. PMA Adaptation Flow
3. Parameter Settings x
3.1. Main Parameters 3.2. PMA Adaptation Parameters
4. Functional Description x
4.1. Interfaces 4.2. IP Clocks 4.3. High Level Data Path Flow for Interlaken Mode 4.4. High Level Data Path Flow for Interlaken Look-aside Mode 4.5. Modes of Operation 4.6. Performance 4.7. IP Core Reset 4.8. M20K ECC Support 4.9. Out-of-Band Flow Control
4.3. High Level Data Path Flow for Interlaken Mode x
4.3.1. Interlaken TX Path 4.3.2. Interlaken RX Path 4.3.3. Unused Transceiver Channels
4.3.1. Interlaken TX Path x
4.3.1.1. Transmit Path Blocks 4.3.1.2. In-Band Calendar Bits on Transmit Side
4.3.2. Interlaken RX Path x
4.3.2.1. Receive Path Blocks 4.3.2.2. In-Band Calendar Bits on Receive Side 4.3.2.3. RX Errored Packet Handling
4.3.2.3. RX Errored Packet Handling x
4.3.2.3.1. Example With Errors and In-Band Calendar Bits
4.4. High Level Data Path Flow for Interlaken Look-aside Mode x
4.4.1. Interlaken Look-aside TX Path 4.4.2. Interlaken Look-aside RX Path
4.4.1. Interlaken Look-aside TX Path x
4.4.1.1. Transmit Path Blocks
4.4.2. Interlaken Look-aside RX Path x
4.4.2.1. Receive Path Blocks 4.4.2.2. RX Error Handling
4.5. Modes of Operation x
4.5.1. Interleaved and Packet Modes 4.5.2. Interlaken Mode 4.5.3. Interlaken Look-aside Mode 4.5.4. Multi-Segment Mode
4.5.2. Interlaken Mode x
4.5.2.1. Transmit User Data Interface Examples 4.5.2.2. Receive User Data Interface Example
4.5.3. Interlaken Look-aside Mode x
4.5.3.1. Transmit User Data Interface Example 4.5.3.2. Receive User Data Interface Example
4.5.4. Multi-Segment Mode x
4.5.4.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals 5.7. External PLL Interface Signals
7. Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode
1. Introduction
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. Register Map
7. Test Features
8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives
9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide

1.3. Performance and Resource Utilization

This section covers the resources and expected performance numbers for selected variations of the Interlaken IP core using the Intel® Quartus® Prime Pro Edition software. The number of ALMs and logic registers are rounded up to the nearest 100. Your results may slightly vary depending on the device you select.

For a comprehensive list of supported configurations, refer to Table: IP Supported Combinations of Number of Lanes and Data Rates.

Table 4.   Intel® Stratix® 10 FPGA Resource Utilization in Interlaken Mode for Multi-segment (Segment = 1)The following numbers are obtained using the Intel® Quartus® Prime Pro Edition software version 23.1.
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs needed Logic Registers M20K Blocks
Primary Secondary
Intel® Stratix® 10 L-tile 4 6.25 10040.6 22756 4397 28
12.5 10451 24481 4291 28
25.28 10626.2 24850 4528 28
25.78 10641.2 25088 4290 28
25.78125 10678.2 24865 4513 28
8 12.5 21314.5 50393 7198 52
10 12.5 27396.2 64351 8235 61
12 10.3125 22278.7 50951 7900 52
12.5 22324.2 50468 8383 52
Intel® Stratix® 10 H-tile 4 6.25 9987.3 22733 4420 28
12.5 10826 24908 4242 28
25.28 10987.1 25326 4314 28
25.78 11023.6 25342 4416 28
25.78125 10975.1 25448 4310 28
6 25.28 21970.8 50223 8288 52
25.78 22014.6 50091 8244 52
25.78125 22039.4 49867 8338 52
8 12.5 22146.7 51028 7322 52
25.28 22602.9 52125 7289 52
25.78 22805 51938 7208 52
25.78125 22554.7 51561 7390 52
10 12.5 27359.4 64348 8238 61
25.28 33726.9 80461 8919 100
25.78 33771.7 80569 8897 100
25.78125 33835.8 80515 8762 100
12 10.3125 23335.9 52147 7902 52
12.5 22419.3 50675 8176 52
25.28 36656.8 87579 10757 100
25.78 36627.3 87612 10511 100
25.78125 36632.3 87399 10336 100
Intel® Stratix® 10 E-tile (NRZ) 4 6.25 15845.2 33309 5889 28
12.5 15889.5 33214 5984 28
25.28 16066.8 33558 5949 28
25.78 16085.5 33477 5995 28
25.78125 16095.9 33763 5806 28
6 25.28 29553.8 62716 10258 52
25.78 29555.9 63118 10122 52
25.78125 29549.8 62773 10506 52
8 12.5 32311.8 68121 10438 52
25.28 32856 68779 10284 52
25.78 32815.7 68692 10257 52
25.78125 32876.6 68301 10257 52
10 12.5 41064.1 87203 11627 61
25.28 46490.5 101748 12810 100
25.78 46489.8 100912 12768 100
25.78125 46486.9 101255 12400 100
12 10.3125 49838.4 105400 13554 73
12.5 48000.2 102967 14031 85
25.28 51991.9 112978 14889 100
25.78 51986.9 113161 14491 100
25.78125 52027.3 112549 14759 100
Intel® Stratix® 10 E-tile (PAM4) 12 26.5625 64881.1 136471 19756 100
Table 5.   Intel® Stratix® 10 FPGA Resource Utilization in Interlaken Mode for Packet ModeThe following numbers are obtained using the Intel® Quartus® Prime Pro Edition software version 23.1.
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs needed Logic Registers M20K Blocks
Primary Secondary
Intel® Stratix® 10 L-tile 4 6.25 10037.1 22746 4411 28
12.5 10474.7 24455 4319 28
25.28 10679.7 24730 4650 28
25.78 10660.4 24826 4459 28
25.78125 10665.4 24817 4563 28
8 12.5 21369.9 50342 7251 52
10 12.5 27366.4 64071 8519 61
12 10.3125 22403 50645 8210 52
12.5 22400.1 50277 8610 52
Intel® Stratix® 10 H-tile 4 6.25 10026.4 22783 4374 28
12.5 10816.7 24837 4315 28
25.28 11030.4 25464 4285 28
25.78 11011 25395 4365 28
25.78125 11084.4 25447 4313 28
6 25.28 22030.7 49993 8265 52
25.78 22042.1 49848 8279 52
25.78125 22017.1 50037 8185 52
8 12.5 22144.2 50953 7399 52
25.28 22675.7 51791 7374 52
25.78 22663.2 52140 6801 52
25.78125 22685.1 51933 7119 52
10 12.5 27376.5 64331 8259 61
25.28 33763.1 80553 8914 100
25.78 33723.7 80501 8849 100
25.78125 33872.5 80714 8629 100
12 10.3125 23331.5 52265 7788 52
12.5 22365.3 50761 8094 52
25.28 36750.6 87540 10719 100
25.78 36805.8 87612 10539 100
25.78125 36665.2 87236 10727 100
Intel® Stratix® 10 E-tile (NRZ) 4 6.25 15861.7 33188 6017 28
12.5 15890.8 33403 5802 28
25.28 16114.6 33463 5982 28
25.78 16114 33522 6021 28
25.78125 16106.7 33192 6084 28
6 25.28 29542.1 62644 10464 52
25.78 29550.5 62464 10258 52
25.78125 29559.1 62862 10430 52
8 12.5 32337 68260 10300 52
25.28 32889.8 68971 10180 52
25.78 32902.7 68697 10204 52
25.78125 32935.2 68653 10281 52
10 12.5 41111.9 86905 11884 61
25.28 46536.9 101281 12992 100
25.78 46494.1 101465 12086 100
25.78125 46540.8 101328 12394 100
12 10.3125 49910.9 105631 13329 73
12.5 48068.3 102792 14183 85
25.28 51994.8 113408 15027 100
25.78 51992.8 113069 14838 100
25.78125 52077.7 112942 15169 100
Intel® Stratix® 10 E-tile (PAM4) 12 26.5625 64867.7 136167 19669 100
Table 6.   Intel® Agilex™ 7 FPGA Resource Utilization in Interlaken Mode for Multi-segment (Segment = 1)The following numbers are obtained using the Intel® Quartus® Prime Pro Edition software version 23.1.
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs needed Logic Registers M20K Blocks
Primary Secondary
Intel® Agilex™ 7 E-tile (NRZ) 4 6.25 15086.6 30564 6507 28
12.5 15082.6 30695 6340 28
25.78 15293.2 31063 6769 28
25.28 15287.4 30887 6976 28
25.78125 15282.1 31090 6733 28
6 25.28 28107.5 58326 12574 52
25.78 28129.1 58638 12372 52
25.78125 28086.9 58751 12302 52
8 12.5 30808.3 61980 12396 52
25.28 31073.1 62829 13101 52
25.78 31083 63025 12952 52
25.78125 31072.5 63110 12704 52
10 12.5 39031.9 79171 14507 61
25.28 43997.6 93244 16371 100
25.78 44060.5 93378 16305 100
25.78125 44046.1 93297 16337 100
12 10.3125 47450 96138 16762 73
12.5 45571 93781 17304 85
25.28 49252.5 103599 19558 100
25.78 49300.3 103953 19187 100
25.78125 49293.9 103784 19363 100
Intel® Agilex™ 7 E-tile (PAM4) 12 26.5625 62126.6 126945 24023 100
Table 7.   Intel® Agilex™ 7 FPGA Resource Utilization in Interlaken Mode for Packet ModeThe following numbers are obtained using the Intel® Quartus® Prime Pro Edition software version 23.1.
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs needed Logic Registers M20K Blocks
Primary Secondary
Intel® Agilex™ 7 E-tile (NRZ) 4 6.25 15120.8 30452 6606 28
12.5 15106.2 30472 6546 28
25.78 15318.9 30925 6986 28
25.28 15327.9 30949 6848 28
25.78125 15303.3 31272 6572 28
6 25.28 28099.7 58435 12551 52
25.78 28144.6 58562 12409 52
25.78125 28120.5 58487 12496 52
8 12.5 30866.6 62082 12299 52
25.28 31174.5 63108 12826 52
25.78 31103 63046 12821 52
25.78125 31120.8 62915 12871 52
10 12.5 39106.9 78650 14978 61
25.28 44130.6 93354 16233 100
25.78 44133 92892 16764 100
25.78125 44088.5 93154 16410 100
12 10.3125 47454.6 96154 16814 73
12.5 45589.9 93860 17202 85
25.28 49333.2 104016 19161 100
25.78 49291.1 104216 18879 100
25.78125 49353.5 103825 19267 100
Intel® Agilex™ 7 E-tile (PAM4) 12 26.5625 62117.5 126586 24247 100
Table 8.   Intel® Stratix® 10 E-tile Resource Utilization Numbers in Interlaken Look-aside ModeThe following numbers are obtained using the Intel® Quartus® Prime Pro Edition software version 23.1.
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs Logic Registers M20 Blocks
Primary Secondary
Intel® Stratix® 10 E-tile ( NRZ) 4 6.25 10209.2 19023 3159 0
12.5 10248.2 18923 3271 0
25.28 10282 18710 3307 0
25.78 10265.8 18868 3123 0
25.78125 10281.3 18918 3276 0
6 25.28 15632.8 28409 4668 0
25.78 15648.9 28334 4727 0
25.78125 15642.2 28500 4554 0
8 12.5 21129.3 38941 6035 0
25.28 21264.5 38624 5998 0
25.78 21257.2 38444 5947 0
25.78125 21294.3 38175 6211 0
10 12.5 27111.6 50536 7355 0
25.28 27278.2 49576 7354 0
25.78 27292.9 49682 7314 0
25.78125 27333.6 49763 7467 0
12 10.3125 33560.7 62095 8855 0
12.5 33406.2 62141 8839 0
25.28 33563.4 61196 8886 0
25.78 33584.3 60956 8858 0
25.78125 33626.3 60958 8602 0
Intel® Stratix® 10 E-tile (PAM4) 12 26.5625 46648.1 85084 12562 0
Table 9.   Intel® Agilex™ 7 E-tile Resource Utilization Numbers in Interlaken Look-aside ModeThe following numbers are obtained using the Intel® Quartus® Prime Pro Edition software version 23.1.
Device Parameters Resource Utilization
Number of Lanes Data/Lane Rate (Gbps) ALMs Logic Registers M20 Blocks
Primary Secondary
Intel® Agilex™ 7 E-tile (NRZ) 4 6.25 9613.1 16997 3795 0
12.5 9614.7 17113 3687 0
25.28 9580 17083 3859 0
25.78 9590.5 17136 3804 0
25.78125 9624.4 17214 3755 0
6 25.28 14568.4 25613 5772 0
25.78 14569.8 25866 5573 0
25.78125 14560 25787 5643 0
8 12.5 19931.6 34799 7287 0
25.28 19863.8 34763 7546 0
25.78 19872.3 34811 7471 0
25.78125 19857.6 34914 7320 0
10 12.5 25445.5 44459 9216 0
25.28 25489.1 44372 9663 0
25.78 25479.7 44365 9710 0
25.78125 25458.8 44631 9463 0
12 10.3125 31234.1 54522 10862 0
12.5 31227.5 54509 10946 0
25.28 31378.1 54474 11263 0
25.78 31349.5 54595 11250 0
25.78125 31336.3 54662 11145 0
Intel® Agilex™ 7 E-tile ( PAM4) 12 26.5625 44022.2 77836 15916 0
Related Information
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