Interlaken (2nd Generation) Intel® FPGA IP User Guide

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ID 683396
Date 8/04/2023
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Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. Parameter Settings 4. Functional Description 5. Interface Signals 6. Register Map 7. Test Features 8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives 9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide
1. Introduction x
1.1. Features 1.2. Device Family Support 1.3. Performance and Resource Utilization 1.4. Flexible Lanes Support 1.5. Round-trip Latency 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing Intel® FPGA IPs 2.2. Generated File Structure 2.3. Specifying the IP Core Parameters and Options 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA 2.6. Integrating Your IP Core in Your Design
2.1. Installing and Licensing Intel® FPGA IPs x
2.1.1. Intel® FPGA IP Evaluation Mode
2.6. Integrating Your IP Core in Your Design x
2.6.1. Pin Assignment 2.6.2. Adding the External PLL 2.6.3. PMA Adaptation Flow
3. Parameter Settings x
3.1. Main Parameters 3.2. PMA Adaptation Parameters
4. Functional Description x
4.1. Interfaces 4.2. IP Clocks 4.3. High Level Data Path Flow for Interlaken Mode 4.4. High Level Data Path Flow for Interlaken Look-aside Mode 4.5. Modes of Operation 4.6. Performance 4.7. IP Core Reset 4.8. M20K ECC Support 4.9. Out-of-Band Flow Control
4.3. High Level Data Path Flow for Interlaken Mode x
4.3.1. Interlaken TX Path 4.3.2. Interlaken RX Path 4.3.3. Unused Transceiver Channels
4.3.1. Interlaken TX Path x
4.3.1.1. Transmit Path Blocks 4.3.1.2. In-Band Calendar Bits on Transmit Side
4.3.2. Interlaken RX Path x
4.3.2.1. Receive Path Blocks 4.3.2.2. In-Band Calendar Bits on Receive Side 4.3.2.3. RX Errored Packet Handling
4.3.2.3. RX Errored Packet Handling x
4.3.2.3.1. Example With Errors and In-Band Calendar Bits
4.4. High Level Data Path Flow for Interlaken Look-aside Mode x
4.4.1. Interlaken Look-aside TX Path 4.4.2. Interlaken Look-aside RX Path
4.4.1. Interlaken Look-aside TX Path x
4.4.1.1. Transmit Path Blocks
4.4.2. Interlaken Look-aside RX Path x
4.4.2.1. Receive Path Blocks 4.4.2.2. RX Error Handling
4.5. Modes of Operation x
4.5.1. Interleaved and Packet Modes 4.5.2. Interlaken Mode 4.5.3. Interlaken Look-aside Mode 4.5.4. Multi-Segment Mode
4.5.2. Interlaken Mode x
4.5.2.1. Transmit User Data Interface Examples 4.5.2.2. Receive User Data Interface Example
4.5.3. Interlaken Look-aside Mode x
4.5.3.1. Transmit User Data Interface Example 4.5.3.2. Receive User Data Interface Example
4.5.4. Multi-Segment Mode x
4.5.4.1. Multi-Segment Interface Example
5. Interface Signals x
5.1. Clock and Reset Interface Signals 5.2. Transmit User Interface Signals 5.3. Receive User Interface Signals 5.4. Management Interface Signals 5.5. Reconfiguration Interface Signals 5.6. Interlaken Link and Miscellaneous Signals 5.7. External PLL Interface Signals
7. Test Features x
7.1. Internal Serial Loopback Mode 7.2. External Loopback Mode
1. Introduction
2. Getting Started
3. Parameter Settings
4. Functional Description
5. Interface Signals
6. Register Map
7. Test Features
8. Interlaken (2nd Generation) Intel® FPGA IP User Guide Archives
9. Document Revision History for Interlaken (2nd Generation) Intel® FPGA IP User Guide

5.3. Receive User Interface Signals

Table 30.  Receive User Interface Signals
Signal Name Feature Support Width (Bits) I/O Direction Description
irx_chan ILK 8 Output Receive logic channel number for the first segment chunk. The IP core supports up to 256 channels. The Interlaken IP core samples this value only when a bit of irx_sop or irx_sob is high and irx_num_valid has a non-zero value.
ILA [Number of lanes-1]
irx_chan1 ILK only 8 Output Receive logic channel number for the second segment chunk. The IP core supports up to 256 channels.

The Interlaken IP core samples this value only when a bit of irx_sob[0] is high and irx_num_valid of the second segment chunk has a non-zero value.

irx_num_valid ILK only Variable Output Indicates the number of valid 64-bit words in the current packet in the current data symbol. The width of the irx_num_valid depends on the parameter number of words.

For single segment,

  • If number of words=4, then width=3 using irx_num_valid[2:0]
  • If number of words=8, then width=8 using irx_num_valid[7:4]
  • If number of words=16, then width=5 using irx_num_valid[9:5]
For multi-segment,
  • If number of words=8, then width=8 using irx_num_valid[7:4] (first segment chunk) and irx_num_valid[3:0] (second segment chunk)
  • If number of words=16, then width=10 using irx_num_valid[9:5] (first segment chunk) and irx_num_valid[4:0] (second segment chunk)
If number of words is equal to 8 and Number of segments is equal to 2:
  • irx_num_valid[7:4] indicates the number of valid words in irx_din_words[511:0]. The value can vary from 4’b0000 to 4’b1000.
  • irx_num_valid[3:0] indicates the number of valid words in irx_din_words[255:0]. The values can vary from 4’b0000 to 4’b0100.
For all non-valid cycles, IP core sets the value of irx_num_valid[7:4] and irx_num_valid[3:0]to 4’b0000.
In the end of burst cycle (irx_eob=1), if the value of irx_num_valid[7:4] is equal to or less than 4'b0100 and the Number of segments parameter is set to 2, you can set the value of irx_num_valid[3:0] from 4'b0000 to 4'b0100. If the value of irx_num_valid[3:0] is not equal to zero, you must set the value of irx_sop[0] or irx_sob[0] to 1'b1.
irx_num_valid[7:4] irx_num_valid[3:0]
1, 2, 3, 4 0, 1, 2, 3, 4
5, 6, 7, 8 0
If number of words is equal to 8 and Number of segments is equal to 4:
  • irx_num_valid[7:4] indicates the number of valid words in irx_din_words[511:0]. The value can vary from 4’b0000 to 4’b1000.
  • irx_num_valid[3:0] indicates the number of valid words in irx_din_words[383:0]. The value can vary from 4'b0000 to 4'b0110.
For all non-valid cycles, the value of irx_num_valid[7:4] and irx_num_valid[3:0] must be set to 4’b0000.
In the end of burst cycle (irx_eob=1), if the value of irx_num_valid[7:4] is equal or less than 4'b0110 and the Number of segments parameter is set to 4, you can set the value of irx_num_valid[3:0] from 4'b0000 to 4'b0110. If the value of irx_num_valid[3:0] is not equal to zero, you must set the value of irx_sop[0] or irx_sob[0] to 1'b1.
irx_num_valid[7:4] irx_num_valid[3:0]
1, 2, 0, 1, 2, 3, 4, 5, 6
3, 4 0, 1, 2, 3, 4
5, 6 0, 1, 2
7, 8 0

If number of words is equal to 16 and Number of segments is equal to 2:

irx_num_valid[7:4] irx_num_valid[3:0]
1, 2, 3, 4, 5, 6, 7, 8 0, 1, 2, 3, 4, 5, 6, 7, 8
9, 10, 11, 12, 13, 14, 15, 16 0
If number of words is equal to 16 and Number of segments is equal to 4:
irx_num_valid[7:4] irx_num_valid[3:0]
1, 2, 3,4 0 to 12
5, 6, 7, 8 0 to 8
9, 10, 11, 12 0 to 4
13, 14, 15, 16 0
irx_eob ILK only 1 Output Indicates the end of the burst (EOB) for the first segment chunk. This signal toggles in Packet Mode and in Interleaved Mode. This signal is not available if you turn on Enable Interlaken Look-aside mode in the Interlaken parameter editor.
irx_eob1 ILK only 1 Output Indicates the end of the burst (EOB) for the second segment chunk.

Only DUAL or QUAD segment interface defines this signal.

irx_eopbits ILK 4 Output Specifies the number of bytes at the end of packet (EOP) for the first segment chunk. Indicates whether the current data symbol contains the EOP with or without an error, and specifies the number of valid bytes in the current end-of-packet, non-error 8-byte data word, if relevant.
IP core sets the value of irx_eopbits as following:
  • 4b’0000: no end of packet, no error.
  • 4b’0001: Error and end of packet.
  • 4b’1xxx: End of packet. xxx indicates the number of valid bytes in the final valid 8-byte word of the packet, as following:
    • 000: all 8 bytes are valid.
    • 001: 1 byte is valid.
    • ...
    • 111: 7 bytes are valid.
All other values (4'b01xx, 4'b001x) are undefined. The valid bytes always start in bit positions [63:56] of the final valid data word of the packet.
ILA [Number of lanes*4 -1:0]

Specifies the number of valid bytes of the corresponding data symbol AND Indicates the end of packet transfer (EOP).

IP core sets the value of itx_eopbits as follows:
  • 4b’0000: no End-of-Packet
  • 4b’0001: Error and End-of-Packet
  • 4b’1xxx: End of packet. xxx indicates the number of valid bytes in the final valid 8-byte word in the burst. Bits [2:0] are encoded as following:
    • 000: all 8 bytes are valid.
    • 001: 1 byte is valid.
    • ...
    • 111: 7 bytes are valid.

All other values (4'b01xx, 4'b001x) are undefined.

irx_eopbits1 ILK only 4 Output Specifies number of bytes at the end of packet (EOP) for the second segment chunk.
You must set the value of irx_eopbits1 as following:
  • 4b’0000: no end of packet, no error.
  • 4b’0001: Error and end of packet.
  • 4b’1xxx: End of packet. xxx indicates the number of valid bytes in the final valid 8-byte word of the packet, as following:
    • 000: all 8 bytes are valid.
    • 001: 1 byte is valid.
    • ...
    • 111: 7 bytes are valid.
All other values (4'b01xx, 4'b001x) are undefined. The valid bytes always start in bit positions [63:56] of the final valid data word of the packet.
irx_sob ILK only 1, 2 or 4 Output Indicates the start of a burst (SOB).

This signal toggles in Packet Mode and in Interleaved Mode. If the IP core is in Interleaved mode, you are responsible for providing the start of the burst signal. If the IP core is in Packet mode, the IP core ignores this signal. The IP core samples the irx_chan signal during this cycle.
  • [1]— single segment
  • [1:0]—dual segment
  • [3:0]—four segment

{segment 3, segment 2, segment 1, segment 0} defines the segment order with segment 3 starts at the most significant bit location (left aligned).

Using four segment as example, the signal has the following valid values:
  • [3]: indicates SOB for the first segment.
  • [2:0]: only one bit can be set to indicate SOB for the second segment.

For example:

If number of words= 16, Number of segments=4, rx_num_valid[9:5]= 3, rx_num_valid[4:0]= 9, then the second segment starts at word[11], sob[3:0]= 4'1100

If number of words= 16, Number of segments=4, rx_num_valid[9:5]= 9, rx_num_valid[4:0]= 4, then the second segment starts at word[3], sob[3:0]= 4'1001

irx_sop ILK 1, 2 or 4 Output Indicates the current data symbol on irx_din_words contains the start of a packet (SOP).
  • [1]— single segment
  • [1:0]—dual segment
  • [3:0]—four segment
{segment 3, segment 2, segment 1, segment 0} defines the segment order with segment 3 starts at the most significant bit location (left aligned).
Using four segment as example, the signal has the following valid values:
  • [3]: indicates SOP for the first segment.
  • [2:0]: only one bit can be set to indicate SOP for the second segment.

For example:

If number of words= 16, Number of segments=4, rx_num_valid[9:5]= 3, rx_num_valid[4:0]= 9, then the second segment starts at word[11], sop[3:0]= 4'1100

If number of words= 16, Number of segments=4, rx_num_valid[9:5]= 9, rx_num_valid[4:0]= 4, then the second segment starts at word[3], sop[0]= 4'1001

ILA [Number of lanes-1:0] Each bit indicates the start of a packet (SOP) for the data burst following corresponding control symbol.
irx_dout_words ILK Variable Output The 64-bit words of input data (one data symbol). The width of the itx_din_words depends on the parameter external_words.
  • If number of words=4, then width=256 bits.
  • If number of words=8, then width=512 bits.
  • If number of words=16, then width=1024 bits.

The first and last data word is in [511:448] and [63:0] respectively. When irx_ num_valid has the value of zero, you should ignore irx_dout_words.

ILA [Number of lanes*64-1:0] The 64-bit words of input data (one data symbol). The width of the itx_din_words depends on the parameter number of lanes.
  • If number of lanes=4, then width=256 bits.
  • If number of lanes=6, then width=284 bits.
  • If number of lanes=8, then width=512 bits.
  • If number of lanes=10, then width=640 bits.
  • If number of lanes=12, then width=768 bits.

For 8 lanes,the first data word is in [511:448] and last data word is in [63:0].

irx_calendar ILK only N * 16 Output Multiple pages (16 bits per page) of calendar input bits. The value is the in-band flow control bits from N control words on the incoming Interlaken link. N is the value of the Number of calendar pages parameter, which can be any of 1, 2, 4, 8. or 16. This signal is synchronous with rx_usr_clk, although it is not part of the user data transfer protocol.
irx_err ILK only 1 Output Indicates an errored packet. This signal is valid only when irx_eob is asserted.
irx_err1 ILK only 1 Output Indicates an errored packet in second segment chunk. This signal is valid only when irx_eob1 is asserted.

This signal is only valid in DUAL or QUAD mode.
irx_ch0_xon ILA only 1 Output Indicates channel 0 flow control.
irx_ch1_xon ILA only 1 Output Indicates channel 1 flow control.
irx_valid ILA only 1 Output Valid signal for entire output bus
irx_idle ILA only [Number of lanes-1:0] Output Each bit indicates unused 64-bit words in the current data symbol and it is also not part of a burst. User logic can ignore the irx_dout_words, irx_sop, irx_eopbits, and irx_chan when irx_idle is equal to one. The irx_idle is equal to one may imply the end of a previous burst.
irx_ctrl ILA only [Number of lanes*29-1:0] Output Eight 29 bits signal indicates the application specific 0 (15 bits), specific 1 (6 bits) and specific 2 (8 bits) data for Interlaken Look-aside mode. This signal can be valid only when irx_sop is asserted. The most significant 29 control bits data is aligned with the most significant bit of irx_sop. {specific 0, specific 1, specific 2} = {[28:14],[13:8],[7:0]}
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