AN 747: Implementing PHYLite in Intel® Arria® 10 Devices Design Examples

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ID 683384
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. AN 747: Altera PHYLite for Parallel Interfaces Loopback Reference Designs Application Note
1. AN 747: Altera PHYLite for Parallel Interfaces Loopback Reference Designs Application Note x
1.1. Simple Input/Output PHYLite Simulation Design Example 1.2. Simple Input/Output PHYLite with Dynamic Reconfiguration Hardware Reference Design 1.3. Functional Description 1.4. Document Revision History
1.1. Simple Input/Output PHYLite Simulation Design Example x
1.1.1. Simulation Design Example Architecture 1.1.2. Simulation Reference Design User Guide 1.1.3. Result
1.1.2. Simulation Reference Design User Guide x
1.1.2.1. Requirements 1.1.2.2. Setting Up the Simulation Environment 1.1.2.3. Running Simulation
1.2. Simple Input/Output PHYLite with Dynamic Reconfiguration Hardware Reference Design x
1.2.1. Hardware Reference Design Architecture 1.2.2. Hardware Design Example User Guide 1.2.3. Result
1.2.2. Hardware Design Example User Guide x
1.2.2.1. System Requirements 1.2.2.2. Setting Up the Development Kit 1.2.2.3. Generating Executable and Linking Format (.elf) Programming File 1.2.2.4. Running the Hardware Reference Design
1.2.3. Result x
1.2.3.1. Dynamic Calibration Result 1.2.3.2. Random Data Transfer Result
1. AN 747: Altera PHYLite for Parallel Interfaces Loopback Reference Designs Application Note

1.2.2.2. Setting Up the Development Kit

The following steps are to setup the Arria 10 FPGA development kit before running the reference design.

  1. Make sure the Arria 10 FPGA development board switches settings are shown as below.
    Figure 11. Switch Settings for Arria 10 FPGA Development Kit
  2. Connect the Intel® FPGA Download Cable to the Arria 10 FPGA development kit and your host machine.
  3. Follow the guidelines in Getting Started with the Design Store to download and install the reference design files.
  4. Open the reference design .qpf file after successfully installing the design templates.
  5. In the Intel® Quartus® Prime software, open dut_INPUT.qsys and dut_OUTPUT.qsys files. Make sure the Altera PHYLite IP core has the configuration shown below:
    Figure 12. Configuration for dut_INPUT Module
    Figure 13. Configuration for dut_OUTPUT Module
  6. Click Tools -> Programmer to program the <project directory> /master_image/top.sof and <project directory>/master_image/max5.pof files into the Arria 10 FPGA development board.
  7. In the <project directory>/core/ folder directory, copy the clk_gui.zip folder to your local machine.
  8. In your local machine Quartus II software installation version 13.1 folder, go to <installation directory>\win64\nios2eds\Nios II Command Shell.bat and execute NIOS II Command Shell.bat.
  9. In the command shell, specify the clk_gui folder path with the command: cd <directory to the copied clk_gui folder>.
  10. Use the command java -jar clk_cont.jar to launch the clock control GUI.
  11. In the clock control GUI, set the target frequency as 50MHz for Si570 (X3) window. Click Set New Frequency.
    Figure 14. Clock Control Setup
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