AN 747: Implementing PHYLite in Intel® Arria® 10 Devices Design Examples

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ID 683384
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
1. AN 747: Altera PHYLite for Parallel Interfaces Loopback Reference Designs Application Note
1. AN 747: Altera PHYLite for Parallel Interfaces Loopback Reference Designs Application Note x
1.1. Simple Input/Output PHYLite Simulation Design Example 1.2. Simple Input/Output PHYLite with Dynamic Reconfiguration Hardware Reference Design 1.3. Functional Description 1.4. Document Revision History
1.1. Simple Input/Output PHYLite Simulation Design Example x
1.1.1. Simulation Design Example Architecture 1.1.2. Simulation Reference Design User Guide 1.1.3. Result
1.1.2. Simulation Reference Design User Guide x
1.1.2.1. Requirements 1.1.2.2. Setting Up the Simulation Environment 1.1.2.3. Running Simulation
1.2. Simple Input/Output PHYLite with Dynamic Reconfiguration Hardware Reference Design x
1.2.1. Hardware Reference Design Architecture 1.2.2. Hardware Design Example User Guide 1.2.3. Result
1.2.2. Hardware Design Example User Guide x
1.2.2.1. System Requirements 1.2.2.2. Setting Up the Development Kit 1.2.2.3. Generating Executable and Linking Format (.elf) Programming File 1.2.2.4. Running the Hardware Reference Design
1.2.3. Result x
1.2.3.1. Dynamic Calibration Result 1.2.3.2. Random Data Transfer Result
1. AN 747: Altera PHYLite for Parallel Interfaces Loopback Reference Designs Application Note

1.2.3.2. Random Data Transfer Result

The result log from the random data transfer process displays the following:
  • The number of words being transferred
  • The sent data value
  • The expected data value
  • The received data value
  • The passing/failing status of the test
Figure 17. Example of Random Data Transfer Result Log
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