AN 919: Improving Quality of Results with Design Assistant

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ID 683369
Date 4/26/2024
Public
Document Table of Contents
Document Table of Contents x
Improving Quality of Results with Design Assistant Document Revision History for AN 919: Improving Quality of Results with Design Assistant Appendix A: Running Design Assistant Appendix B: Design Assistant Rules
Improving Quality of Results with Design Assistant x
About Design Assistant About the Design Assistant Design Example Fixing SDC and CDC Rules in the Design Assistant Design Example Fixing Other Faults in the Design Assistant Design Example
Appendix A: Running Design Assistant x
Running Design Assistant
Appendix B: Design Assistant Rules x
Timing Closure Rules Clock Domain Crossing and Reset Domain Crossing Rules Intrinsic Margin Rules Combinatorial Logic Levels Reducing High Fan-out Nets Hyper-Retimer Restrictions Initial Power-Up Conditions Rules Reset Release Intel FPGA IP
Reducing High Fan-out Nets x
Duplication Rules Tension and Span Rules
Initial Power-Up Conditions Rules x
Removing Initial Power-Up Conditions
Improving Quality of Results with Design Assistant
Document Revision History for AN 919: Improving Quality of Results with Design Assistant
Appendix A: Running Design Assistant
Appendix B: Design Assistant Rules

Reducing High Fan-out Nets

High fan-out nets are difficult to place optimally and can reduce the fMAX of your design. They often lead to congestion and can result in long-path and short-path imbalances that limits retiming in critical chains. While these signals may not be critical, they can span large distances and warp the optimization of other paths around them.
  1. Ensure you duplicate high fan-out driver registers:
    • Use the DUPLICATE_REGISTER and DUPLICATE_HIERARCHY_DEPTH assignments for automated solutions or
    • Edit the RTL to create duplicate copies.
    • If you edit the RTL, apply the preserve_syn_only attribute to the duplicate registers, and assign the duplicates to individual instances in the fan-out hierarchy.
    The compiler automatically promotes recognized high fan-out nets to the global clock network. It also makes a higher optimization effort during place and route stages to duplicate registers.
  2. Set Quartus® Prime to automatically create duplicate register trees based on estimated physical proximity or based on hierarchy.
    1. Apply the following QSF assignment to duplicate registers based on estimated physical proximity:
      set_instance_assignment -name DUPLICATE_REGISTER -to <register name> <num duplicates>

      Where register_name is the name of the register being duplicated and num_duplicates is the number of duplicates to create, including the original.

      Quartus® Prime creates duplicates during the fitter stage and assigns fan-outs based on early estimates of physical distance from their destinations.
    2. Apply the following QSF assignment to perform duplications using hierarchy information:
      set_instance_assignment -name DUPLICATE_HIERARCHY_DEPTH -to <register_name> <level_number>
      Where:
      • Register name is the last register in the chain that fans out to multiple hierarchies
      • Level number is the number of registers in the chain to duplicate.
  3. Typically, set up a synchronous reset tree. Resets are often a significant source of high fan-out nets. The registers in the chain must satisfy the following conditions to be included in duplication:
    1. Only another register must feed registers.
    2. Combinatorial logic must not feed registers.
    3. Registers must not be part of a synchronizer chain.
    4. Registers must not have any secondary signals.
    5. Registers must not have a preserve attribute or a PRESERVE_REGISTER assignment.
    6. All registers in the chain except the last one must have only one fan-out.

Section Content
Duplication Rules
Tension and Span Rules

Level Two Title