Intrinsic Margin Rules
Identifies paths with impossible requirements. Any given datapath in the design has an intrinsic margin that doesn’t depend on place and route but which the design’s RTL and SDCs determine. The clock relationship between launch and latch clocks, clock uncertainty, and by uTsu and Tco time drive these intrinsic margin rules.
The Intrinsic margin rules help diagnose why a path may be failing setup timing. For example, too much clock skew, routing delay, or too many logic levels. Timing violations might not violate these rules, but if they do, they provide guidance on what you can do to fix them.
| Rule | Description | Possible course of action |
|---|---|---|
| TMC-20200 | Setup-Failing Paths with Impossible Requirements These paths have a tight clock relationship. Large differences in uTsu, uTco, and, or significant clock source uncertainty cause failures before any additional delay is added. |
Fix SDC constraints. Ensure hard blocks are registered. Investigate clock sources. |
| TMC-20201 | Setup-Failing Paths with High Clock Skew These paths have such high clock skew that they fail without any contribution from the datapath. |
Apply clock region assignments. Redesign CDCs. |
| TMC-20202 | Setup-Failing Paths with High Cell and Local Interconnect Delay These paths have such high cell delay that they fail without any contribution from the clock network or interconnect. |
Reduce logic levels. Unblock retiming optimizations. |
| TMC-20203 | Setup-Failing Paths with High Fabric Interconnect Delay The path has such high interconnect delay that it fails timing without any contribution from the clock network or datapath logic.
|
Reduce congestion. Apply floorplanning. Restructure RTL to ensure tighter packing. |