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Ixiasoft
About the Design Assistant Design Example
Common user errors can result in on-board failures. This design shows those mistakes and how you catch them with Design Assistant.
The design contains two modules, each in a different clock domain. The design contains high fan-out signals, some congestion, and is missing Synopsis design constraints (SDCs) and proper clock domain crossing. By fixing these issues and adding some hyper-pipelining, the design can meet timing.
Download the design (an919.zip) from www.intel.com.
The design example consists of the following directories:
- base – the original design
- intermediate – the original design and fixes for SDC, CDC, RDC
- final – the intermediate design and additional optimizations
Each directory has the following files:
- top.qpf – project file
- top.qsf – Intel Quartus Prime settings file
- top.sv – top-level Verilog HDL file
- top_clk1.sv – submodule on one of the two clock domains
- top_clk2.sv – submodule on the other clock domain
- byte_enabled_simple_dual_port_ram.v – dual-port RAM
- top.out.sdc – SDC file
The final RTL directory also contains reset_release.ip and clock_control.ip files.
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