Ethernet Link Inspector User Guide for Intel® Stratix® 10 Devices

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ID 683367
Date 7/01/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview of Ethernet Link Inspector for Intel® Stratix® 10 Devices 2. Setting Up the Ethernet Link Inspector 3. Functional Description 4. Ethernet Link Inspector User Guide Archives 5. Document Revision History for the Ethernet Link Inspector User Guide for Intel® Stratix® 10 Devices
1. Overview of Ethernet Link Inspector for Intel® Stratix® 10 Devices x
1.1. Features 1.2. Supported IP Cores and Devices
1.1. Features x
1.1.1. Link Monitor 1.1.2. Link Analysis
2. Setting Up the Ethernet Link Inspector x
2.1. System Requirements and Prerequisites 2.2. Running the Ethernet Link Inspector
2.1. System Requirements and Prerequisites x
2.1.1. System Requirements 2.1.2. Enabling Your Design For the Link Monitor
2.2. Running the Ethernet Link Inspector x
2.2.1. Running the Link Monitor 2.2.2. Running the Link Analysis
2.2.2. Running the Link Analysis x
2.2.2.1. Creating and Capturing Signal Tap File and Exporting Signal Tap Database as CSV File
3. Functional Description x
3.1. Link Monitor Module 3.2. Link Analysis Module
3.1. Link Monitor Module x
3.1.1. Link Monitor Tabs and Settings
3.2. Link Analysis Module x
3.2.1. Sequencer State Machine 3.2.2. Link Analysis Tabs and Settings
3.2.2. Link Analysis Tabs and Settings x
3.2.2.1. Sequencer State Machine Tab 3.2.2.2. Auto Neg Tab 3.2.2.3. Link Training Tab 3.2.2.4. Data Mode Tab 3.2.2.5. Help Tab
1. Overview of Ethernet Link Inspector for Intel® Stratix® 10 Devices
2. Setting Up the Ethernet Link Inspector
3. Functional Description
4. Ethernet Link Inspector User Guide Archives
5. Document Revision History for the Ethernet Link Inspector User Guide for Intel® Stratix® 10 Devices

3.1.1. Link Monitor Tabs and Settings

The Link Monitor module of the Ethernet Link Inspector has three tabs. Each tab implements various Control and Status Registers (CSR) of the selected Ethernet IP core. There is also a Continuous Read All Registers option, which continuously polls the status of all the tabs.

Table 3.  Link Monitor GUI Tabs
Tab Description
MAC & PCS

Resets the IP core, reads the MAC configuration and checks the high level PCS status.

  • Resets: Implements the RESET register.
  • MAC Status: Shows the status of TX MAC registers and RX MAC registers.
  • PCS Status: Shows the status of PCS registers.
  • FEC Status: Shows the status of FEC registers.
Statistics
  • Displays MAC statistics registers for TX and RX traffic.
  • Displays FEC statistics.
PMA
  • Displays KR/KR4 registers that includes Auto Negotiation and Link Training.
  • Displays PMA parameters such as differential output voltage (VOD), continuous time linear equalizer (CTLE), distributed feedback equalizer (DFE), and etc.
Help Displays link bring up guidelines

The following figures show the Link Monitor GUI tabs and are related to the 25G E-tile Hard IP for Ethernet Intel® FPGA IP. The availability of each tab depends on IP selection and its features.

Figure 2. Example MAC & PCS Tab
Figure 3. Example Statistics Tab
Figure 4. Example PMA Tab
Figure 5. Example Help TabThe Read/Write Register section allows you to read and write values from and to the registers. Register address starts with 0x followed by the effective address. The address includes base address, word offset, and channel offset.
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