Ethernet Link Inspector User Guide for Intel® Stratix® 10 Devices

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ID 683367
Date 7/01/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview of Ethernet Link Inspector for Intel® Stratix® 10 Devices 2. Setting Up the Ethernet Link Inspector 3. Functional Description 4. Ethernet Link Inspector User Guide Archives 5. Document Revision History for the Ethernet Link Inspector User Guide for Intel® Stratix® 10 Devices
1. Overview of Ethernet Link Inspector for Intel® Stratix® 10 Devices x
1.1. Features 1.2. Supported IP Cores and Devices
1.1. Features x
1.1.1. Link Monitor 1.1.2. Link Analysis
2. Setting Up the Ethernet Link Inspector x
2.1. System Requirements and Prerequisites 2.2. Running the Ethernet Link Inspector
2.1. System Requirements and Prerequisites x
2.1.1. System Requirements 2.1.2. Enabling Your Design For the Link Monitor
2.2. Running the Ethernet Link Inspector x
2.2.1. Running the Link Monitor 2.2.2. Running the Link Analysis
2.2.2. Running the Link Analysis x
2.2.2.1. Creating and Capturing Signal Tap File and Exporting Signal Tap Database as CSV File
3. Functional Description x
3.1. Link Monitor Module 3.2. Link Analysis Module
3.1. Link Monitor Module x
3.1.1. Link Monitor Tabs and Settings
3.2. Link Analysis Module x
3.2.1. Sequencer State Machine 3.2.2. Link Analysis Tabs and Settings
3.2.2. Link Analysis Tabs and Settings x
3.2.2.1. Sequencer State Machine Tab 3.2.2.2. Auto Neg Tab 3.2.2.3. Link Training Tab 3.2.2.4. Data Mode Tab 3.2.2.5. Help Tab
1. Overview of Ethernet Link Inspector for Intel® Stratix® 10 Devices
2. Setting Up the Ethernet Link Inspector
3. Functional Description
4. Ethernet Link Inspector User Guide Archives
5. Document Revision History for the Ethernet Link Inspector User Guide for Intel® Stratix® 10 Devices

3.2.2.4. Data Mode Tab

Data Mode tab may have one or more subtabs based on number of times the device go into Data Mode state during the Signal Tap capture in a finite amount of time. Each subtab displays the Ethernet IP link behavior during the occurrence of Data Mode. Each Data Mode occurrence is also prefixed with a number to distinguish between various Data Mode occurrences.

Table 16.  Local Device Status Signals
Name Signal Indication Description
For 10GBASE-KR Intel® Stratix® 10 FPGA IP:
RX Block Lock rx_block_lock LED
  • Green: Locked from receiving Ethernet packets. Also shows the timestamp of lock.
  • Red: Not locked from receiving Ethernet packets.
RX Data Ready rx_data_ready LED
  • Green: Represents successful block lock assertion. Also shows the timestamp. an_done will be asserted.
  • Red: Block lock not asserted.
FEC pcs_mode_rc LED
  • Green: Local device is using FEC.
  • Red: Local device is not using FEC.
For Intel® Stratix® 10 Low Latency 40G Ethernet Intel® FPGA IP:
PCS Align Lock rpcs_align_locked LED
  • Green: All 4 lanes are skew compensated and aligned. Also shows the timestamp of lock.
  • Red: Lanes are not skew compensated and not aligned.
PCS Deskew Lock rpcs_deskew_locked LED
  • Green: All 4 lanes are locked for alignment marker. Also shows the timestamp of lock.
  • Red: Lanes are not locked for alignment marker.
FEC pcs_mode_rc LED
  • Green: Local device is using FEC.
  • Red: Local device is not using FEC.
PCS Word Lock rpcs_word_locked LED This signal is available per channel basis. There are four signals for 40GBASE-KR.
  • Green: Locked from receiving Ethernet packets.
  • Red: Not locked from receiving Ethernet packets.
RX ENH Block Lock rx_enh_blk_lock LED This signal is available per channel basis. There are four signals for 40GBASE-KR.
  • Green: FEC is locked from receiving Ethernet packets.
  • Red: FEC is not locked from receiving Ethernet packets.
For Intel® Stratix® 10 H-Tile Hard 50G and 100G IPs:
RX Alignment Market Lock o_rx_am_lock LED
  • Green: All 4 lanes locked to the alignment marker.
  • Red: Lanes not locked to the alignment marker.
RX Block Lock o_rx_block_lock LED
  • Green: All 4 lanes locked to the incoming 64b/66b.
  • Red: Lanes not locked to the incoming 64b/66b.
For Intel® Stratix® 10 Low Latency 100G Ethernet Intel® FPGA IP:
PCS Align Lock align_locked LED
  • Green: All 4 lanes are skew compensated and aligned. Also shows the timestamp of lock.
  • Red: Lanes are not skew compensated and not aligned.
PCS Deskew Lock deskew_locked LED
  • Green: All 4 lanes are locked for alignment marker. Also shows the timestamp of lock.
  • Red: Lanes are not locked for alignment marker.
FEC pcs_mode_rc LED
  • Green: Local device is using FEC.
  • Red: Local device is not using FEC.
PCS Word Lock word_locked LED
  • Green: Locked from receiving Ethernet packets.
  • Red: Not locked from receiving Ethernet packets.
Table 17.  Data Mode Status Signals
Signal Indication Description
For 10GBASE-KR Intel® Stratix® 10 FPGA IP:
rx_block_lock Waveform Displays the behavior of rx_block_lock in time domain. When asserted, it indicates that the local device is locked from receiving Ethernet packets. This is a waveform representation of the RX Block Lock signal in the Table 16.
rx_data_ready Waveform Displays the behavior of rx_data_ready in time domain. This represents a successful block lock assertion. This is a waveform representation of the RX Data Ready signal in the Table 16.
rx_hi_ber Waveform

Displays if the device receives invalid sync header for more than 16 times within 125 us time period, as defined in Clause 49 of the IEEE 802.3 2015 Standard.

For Intel® Stratix® 10 Low Latency 40G Ethernet Intel® FPGA IP:
rpcs_align_locked Waveform Displays the behavior of rpcs_align_locked in time domain. When asserted, it indicates that all 4 lanes are skew compensated and aligned. This is a waveform representation of the PCS Align Lock signal in the Table 16.
rpcs_deskew_locked Waveform Displays the behavior of rpcs_deskew_locked in time domain. When asserted, it indicates that all 4 lanes are locked to alignment markers. This is a waveform representation of the PCS Deskew Lock signal in the Table 16.
rx_hi_ber Waveform

Displays if device receives invalid sync header for more than 16 times within 125 us time period, as defined in Clause 49 of the IEEE 802.3 2015 Standard.

rpcs_word_locked Waveform Displays the behavior of rpcs_word_locked in time domain. When asserted, it indicates that the local device is locked from receiving Ethernet packets. This is a waveform representation of the PCS Word Lock signal in the Table 16.
rx_enh_blk_lock Waveform Displays the behavior of rx_enh_blk_lock in time domain. When asserted, it indicates that FEC is locked from receiving Ethernet packets. This is a waveform representation of the RX ENH Block Lock signal in the Table 16.
For Intel® Stratix® 10 H-Tile Hard 50G and 100G IPs:
o_rx_hi_ber Waveform Displays if the local device receives invalid sync header for more than 16 times within 125 us time period, as defined in Clause 49 of the IEEE 802.3 2015 Standard.
o_rx_am_lock Waveform Displays the behavior of o_rx_am_lock in time domain. When asserted, it indicates that the local device is locked to alignment markers. This is a waveform representation of the RX Alignment Marker Lock signal in the Table 16.
o_rx_block_lock Waveform Displays the behavior of o_rx_block_lock in time domain. When asserted, it indicates that the local device is locked to the 64b/66b blocks from receiving Ethernet packets. This is a waveform representation of the RX Block Lock signal in the Table 16.
For Intel® Stratix® 10 Low Latency 100G Ethernet Intel® FPGA IP:
align_locked Waveform

Displays the behavior of align_locked in time domain. When asserted, it indicates that all 4 lanes are skew compensated and aligned. This is a waveform representation of the PCS Align Lock signal in the Table 16.

deskew_locked Waveform Displays the behavior of deskew_locked in time domain. When asserted, it indicates that all 4 lanes are locked to alignment markers. This is a waveform representation of the PCS Deskew Lock signal in the Table 16.
rx_hi_ber Waveform Displays if device receives invalid sync header for more than 16 times within 125 us time period, as defined in Clause 49 of the IEEE 802.3 2015 Standard.
word_locked Waveform Displays the behavior of word_locked in time domain. When asserted, it indicates that the local device is locked from receiving Ethernet packets. This is a waveform representation of the PCS Word Lock signal in the Table 16.
Table 18.  Device Intrinsic Signals
Note: This table displays the device internal signals used mostly for debugging purpose. Contact Intel® Premier Support for any questions related to these signals.
Signal Indication Description
rx_is_lockedtodata Waveform Shows if clock data recover (CDR) receiver of the Local Device is locked to the incoming data. This is different than rx_is_lockedtodata coming from CDR. This is asserted only when CDR is locked to data for 1 ms.
rx_is_lockedtoref Waveform Shows if CDR receiver of the Local Device is locked to a reference clock.
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