2.5. Compiling and Testing the Design
Perform the following steps to compile the design and program the development board:
- Launch the Intel® Quartus® Prime software and compile the design ( ).
The timing constraints and pin assignments for the design example and the design components are automatically loaded during design example compilation.
- Connect the development board to the host computer either by connecting a USB cable to the on-board Intel® FPGA Download Cable II component or using an external Intel® FPGA Download Cable II module to connect to the external JTAG connector.
- Launch the Clock Control application that is included with the development board, and set the clock settings according to the selected data rate.
Note: Refer to the Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit User Guide for more information about using the Clock Control application.
Table 8. Clock Settings Clock Name Clock Frequency refclk_xcvr Select the frequency for the transceiver PLL reference clock in the IP parameter editor. refclk_core Select the frequency for the core PLL reference clock in the IP parameter editor. mgmt_clk 100 MHzFigure 5. Intel® Stratix® 10 TX Signal Integrity Development Kit (Revision A or Revision B) Clock Control GUI SettingThis example shows the clock control GUI setting for a design example running at 24.333 Gbps on an E-tile device using Intel® Stratix® 10 TX Transceiver Signal Integrity Development Kit (applies to Revision A and Revision B).
- If you are performing external loopback test for designs targeting Intel® Stratix® 10 TX Signal Integrity Development Kit (E-tile), attach the respective loopback module according to the board revision:
- For engineering sample (ES) edition (Revision A), attach the QSFP-DD loopback module at the QSFP-DD 1x2 connector. Refer to Board Connectivity for information on which QSFP-DD 1x2 connectors to attach the module.
- For production edition (Revision B), attach the FMC+ loopback module at the FMC+ connector.
- Configure the FPGA on the development board with the generated programming file (.sof file) using the Intel® Quartus® Prime Programmer.