E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

ID 683357
Date 10/02/2023
Public
Give Feedback

2.4. Compiling and Simulating the Design

The design example testbench simulates your generated design.

To simulate the design, perform the following steps:

  1. Change the working directory to <example_design_directory>/simulation/<Simulator>.
  2. In the command line, run the simulation script. The table below shows the commands to run the supported simulators.
    Simulator Command

    ModelSim*

    QuestaSim*

    vsim -do modelsim_sim.tcl
    vsim -c -do modelsim_sim.tcl (without ModelSim* or QuestaSim* GUI)
    VCS* sh vcs_sim.sh
    VCS* MX sh vcsmx_sim.sh
    Xcelium* Parallel sh xcelium_sim.sh
    The simulation ends with messages that indicate whether the run was successful or not.
    Figure 4. Successful SimulationThe average simulation run time is about 30 minutes.