E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

Download PDF
ID 683357
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide 2. JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the JESD204C Design Example 4. E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the JESD204C Design Example x
3.1. System Components 3.2. JESD204C Design Example Clock and Reset 3.3. JESD204C Design Example Signals 3.4. JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. SYSREF Generator 3.1.5. Pattern Generator and Checker
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the JESD204C Design Example
4. E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

5. Document Revision History for the E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2023.10.02 23.3 3.1.1
  • Updated Steps: Compiling and Testing the Design to remove bonded mode support.
  • Updated Table: Intel® Stratix® 10 TX Signal Integrity Development Kit Board Connectivity to remove bonded mode support.
  • Updated document title from JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide to E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide.
  • Updated "Intel® Agilex™" product family name to "Intel Agilex® 7".
2022.10.21 22.3 1.1.0
  • Updated Figure: Intel® Stratix® 10 TX Signal Integrity Development Kit (Revision B) Clock Control GUI Setting for Bonded Mode Design.
  • Updated Steps: Compiling and Testing the Design.
  • Updated Table: Intel® Stratix® 10 TX Signal Integrity Development Kit Board Connectivity.
  • Updated the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives section.
2021.11.22 21.3 1.1.0 Updated Compiling and Testing the Design to include related information about running the hardware testing using the Tcl script.
2021.11.01 21.3 1.1.0 Updated the JESD204C Intel® Stratix® 10 FPGA IP Design Example Quick Start Guide chapter:
  • Added support for QuestaSim* simulator.
  • Removed references to the NCSim simulator.
2021.01.07 20.4 1.1.0
  • Updated the Compiling and Testing the Design and Board Connectivity sections with the latest information for design examples with bonded and non-bonded mode configurations.
  • Removed the Clock Control GUI column in Table: Clock Settings.
2020.10.05 20.3 1.1.0
  • Updated the change in board information for Intel® Stratix® 10 E-tile devices in the Compiling and Testing the Design and Board Connectivity sections.
2020.04.20 19.4 1.1.0
  • Updated the Compiling and Testing the Design section with new information about the clock settings.
  • Updated the Board Connectivity section with latest information for the refclk_core and mgmt_clk ports.
  • Updated the description for the tst_ctl register in the JESD204C Design Example Control Registers section and the Test pattern parameter in the Design Example Parameters section. Starting Intel® Quartus® Prime Pro Edition software version 19.3 onwards, you can no longer use the [1:0] bit of the test control register to change the PRBS pattern. Use the Test pattern parameter instead.
2019.12.16 19.4 1.1.0
  • Updated the related document links and the acronyms, glossary, and symbols lists in the About the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide section.
  • Updated the files and folders in the Directory Structure section.
  • Added an alternative command for the ModelSim* simulator in the Compiling and Simulating the Design section.
  • Edited the JESD204C design example block diagram to remove multilink implementation the Design Example Block Diagram section. Multilink implementation will be supported in a future release.
  • Edited the information in the following sections for better clarity.
    • JTAG to Master Bridge
    • Parallel I/O (PIO) Core
    • SPI Master
    • SYSREF Generator
    • Pattern Generator and Checker
  • Edited the descriptions and the timing diagram for the design example clocks and resets in the JESD204C Design Example Clock and Reset section.
  • Edited the descriptions for the design example registers in the JESD204C Design Example Control Registers section.
2019.08.01 19.2 1.0.0 Initial release.
Level Two Title