Intel® High Level Synthesis Compiler Pro Edition: Reference Manual

ID 683349
Date 12/19/2022

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3.1. Supported C and C++ Subset for Component Synthesis

Some common software patterns cannot be physically realized in FPGA digital logic, which results in limitations in the coding style that the Intel® HLS Compiler can support.
The compiler cannot generate RTL for the following C++ constructs:
  • Dynamic memory allocation.
  • Virtual functions.
  • Function pointers
  • C++ or C library functions, except the supported math functions explicitly mentioned in Supported Math Functions.
  • Non-static class functions.
  • Template functions without an explicit specialization.
In general, the compiler can generate RTL for functions that can be statically linked such as static class methods and "regular" functions. HLS component functions can include classes, structs, functions, templates, and pointers.

In addition, a component or task function cannot contain an irreducible loop. That is, loops in component and task functions must have only one entry point into the loop.

Important: These synthesis limitations do not apply to testbench code.