Intel® High Level Synthesis Compiler Pro Edition: Reference Manual

ID 683349
Date 12/19/2022

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13.1. Intel® HLS Compiler Pro Edition i++ Command-Line Arguments

Use the i++ command-line arguments to affect how your component is compiled and linked.

General i++ Command Options

Option Description
--debug-log Generate the compiler diagnostics log.
-h, --help List compiler command options along with brief descriptions.
-o result Place compiler output into the <result> executable and the <result>.prj directory.
-v Display messages describing the progress of the compilation.
--version Display compiler version information.

Command Options Affecting Compiling

Option Default Value Description
-c Preprocess, parse, and generate object files.
--component component name Comma-separated list of function names to compile to RTL.
To use this option, your component must be configured with C-linkage using the extern "C" specification. For example:
extern "C" int myComponent(int a, int b)

Using the component function attribute is preferred over using the --component command option to indicate functions that you want the compile to RTL.

-D macro [= val ] Define a <macro> with <val> as its value.
-g   Generate debug information (default option).
-g0   Do not generate debug information.

Specifies the path to a GCC installation that you want to use for compilation. This path should be the absolute path to the directory that contains the GCC lib, bin, and include folders.

--hyper-optimized-handshaking=[auto|off] auto

This option applies to Intel® Agilex™ and Intel® Stratix® 10 devices only.

Use this option to modify the handshaking protocol used in certain areas of your design.

-I dir Add directory <dir> to the end of the main include path.
-march=[x86-64 | FPGA_family | FPGA_part_number] x86-64 Generate code for an emulator flow (x86-64) or for the specified FPGA family or FPGA part number.
--quartus-compile Run the HDL generated through Intel® Quartus® Prime to generate accurate fMAX and area estimates. Your component is not expected to cleanly close timing.
--quartus-seed <seed>   Specifies the Fitter seed to use when your component is compiled to hardware by Intel® Quartus® Prime.
--simulator simulator_name modelsim Specifies the simulator you are using to perform verification.
This command option can take the following values for <simulator_name>:
Use Siemens* EDA ModelSim* or Questa* for component verification.
Disable verification. That is, generate RTL for components without the test bench.

If you do not specify this option, --simulator modelsim is assumed.

-ffp-contract=[ fast | on ]

  For double-precision data types, controls whether the compiler can contract floating-point multiply and add or subtract operations into a single fused multiply-add (FMA), and controls whether the compiler skips intermediate rounding and conversions, except for code blocks fenced by #pragma clang fp contract(off).

This option has no effect on operations that involve single-precision data types.

The -ffp-contract option can take one of the following values:
Math operations can be fused across multiple adjacent lines of code.

Math operations in code fenced by #pragma clang fp contract(on) can be fused only across a single line of code.

Math operations can be fused only across a single line of code.

Math operations in code fenced by #pragma clang fp contract(fast) can still be fused across multiple adjacent lines of code.

To learn more, review the following tutorials:
  • <quartus_installdir>/hls/examples/tutorials/best_practices/floating_point_contract
  • <quartus_installdir>/hls/examples/tutorials/best_practices/floating_point_ops


  Relax the order of floating point arithmetic operations, except for code blocks fenced by #pragma clang fp reassociate(off)

To learn more, review the following tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/floating_point_ops

--daz   For double data types only, disable subnormal support in double-precision floating-point computations.
--rounding= [ieee | faithful]  

For double data types only, control rounding scheme for double-precision adders, multipliers, and dividers.

If you do not specify this option, adders and multipliers use IEEE-754 round to nearest, ties to even (RNE) rounding (0.5 ULP) and dividers uses faithful rounding (1 ULP).

The -rounding option can take one of the following values:
All adders, multipliers, and dividers use IEEE-754 RNE rounding.

IEEE-754 RNE rounding rounds results to the nearest value. If the number falls midway, it is rounded to the nearest value with an even least-significant digit. This is the default rounding mode defined by IEEE 754-2008 standard.

All adders, multipliers, and dividers use faithful rounding.

Faithful rounding rounds results to either the upper or lower nearest single-precision numbers. Therefore, faithful rounding produces one of two possible values. The choice between the two is not defined.

Faithful rounding has a maximum error of one ULP. Errors are not guaranteed to be evenly distributed.

Faithful rounding mode is not defined by the IEEE-754 standard.

--clock clock target 240 MHz Optimize the RTL for the specified clock frequency or period.

The clock target value must include a unit.

For example:
i++ -march="Arria 10" test.cpp --clock 100MHz
i++ -march="Arria 10" test.cpp --clock 10ns
--dsp_mode= [prefer-dsp | prefer-softlogic | default] default For supported data types and math operations, controls the hardware implementation of math functions on a global scope.
The compiler tries to implement supported math operations with DSPs.
The compiler tries to implement supported math operations with soft logic using ALMs.
The compiler implements supported math operations with DSP blocks or soft logic (ALMs) based on data type and operation.

This value is the default.

For details about the implementation of math functions in hardware, refer to Math Function Hardware Implementation Summary.

To learn more, refer to the following tutorial: <quartus_installdir>/hls/examples/tutorials/best_practices/control_of_dsp_usage

Command Options Affecting Linking

Option Default Value Description
-ghdl[=<depth>] Enable full debug visibility and logging of HDL signals in simulation.

Use the optional <depth> attribute to specify how many levels of hierarchy are logged. If you do not specify a value for the <depth> attribute, all signals are logged.

Use -ghdl=1 to log only the top-level signals.

-L dir

-L dir

(Linux only) Add directory <dir> to the list of directories to be searched for library files specified with the -l option.
-l library (Linux only) Use the library name <library> when linking.
--x86-only   Create only the testbench executable ( <result>.out/ <result>.exe).
--fpga-only   Create only the <result>.prj directory and its contents.