DSP Builder for Intel® FPGAs (Advanced Blockset): Handbook

ID 683337
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

9.1.2. ALU Folding Parameters

Table 26.  ALU Folding Parameters
Parameter Description
Sample Rate Data sample rate.
Number of Channels Supports single or multiple channels
Maximum latency Maximum latency for the system.
Register outputs The format of data outputs
Simulation rate Specify clock rate or data rate to control how Simulink models the system