2. About DSP Builder for Intel® FPGAs
You can create designs without needing detailed device knowledge and generate designs that run on a variety of FPGA families with different hardware architectures. DSP Builder allows you to manually describe algorithmic functions and apply rule-based methods to generate hardware optimized code. The advanced blockset is particularly suited for streaming algorithms characterized by continuous data streams and occasional control. For example, use DSP Builder to create RF card designs that comprise long filter chains.
After specifying the desired clock frequency, target device family, number of channels, and other top-level design constraints, DSP Builder pipelines the generated RTL to achieve timing closure. By analyzing the system-level constraints, DSP Builder can optimize folding to balance latency versus resources, with no need for manual RTL editing.
DSP Builder advanced blockset includes its own timing-driven IP blocks that can generate high performance FIR, CIC, and NCO models.
DSP Builder is interoperable with other Simulink blocksets. In particular, you can use the basic Simulink blockset to create interactive testbenches. The automatic testbenches allow you to compare Simulink simulation results with the output of the ModelSim simulator that simulates the HDL generated for your DSP Builder design.
You can run the ModelSim simulator from within DSP Builder, if the ModelSim executable is in your path. The automatic testbench flow generates and runs a test script that returns a result indicating whether or not the outputs match.
Intel Quartus Prime
DSP Builder allows you to build high-speed, high-performance DSP datapaths. In most production designs there is an RTL layer surrounding this datapath to perform interfacing to processors, high speed I/O, memories, and so on. To complete the design, use Platform Designer or RTL to assign board level components. Intel Quartus Prime can then complete the synthesis and place-and-route process. You can automatically load a design into Intel Quartus Prime by clicking on the Run Quartus Prime block in the top-level model.
DSP Builder creates a conduit interface and hw.tcl file for each advanced blockset design. It creates a memory-mapped interface only if the design contains interface blocks or external memory blocks. It can also create an Avalon® Streaming interface. The hw.tcl file can expose the processor bus for connection in Platform Designer. A DSP Builder subsystem is available from the System Contents tab in Platform Designer after you add the path to the hw.tcl file to the Platform Designer IP search path