Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide
ID
683335
Date
4/09/2025
Public
1. Quick Start Guide
2. Detailed Description for Stratix® V Serial Lite III Streaming Standard Clocking Mode
3. Detailed Description for Stratix® V Serial Lite III Streaming Advanced Clocking Mode
A. Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide Archives
B. Document Revision History for the Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide
1.3. Generating the Design
You can use the Serial Lite III Streaming IP core parameter editor in the Quartus® Prime software to generate the design example.
Figure 4. Procedure
Figure 5. Example Design Tab
Figure 6. Generation Window