Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide

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ID 683335
Date 4/09/2025
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Detailed Description for Stratix® V Serial Lite III Streaming Standard Clocking Mode 3. Detailed Description for Stratix® V Serial Lite III Streaming Advanced Clocking Mode A. Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide Archives B. Document Revision History for the Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Example Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design
1.3. Generating the Design x
1.3.1. Procedure 1.3.2. Design Example Parameters 1.3.3. Presets
1.4. Simulating the Design x
1.4.1. Procedure
2. Detailed Description for Stratix® V Serial Lite III Streaming Standard Clocking Mode x
2.1. Features 2.2. Hardware and Software Requirements 2.3. Functional Description 2.4. Simulation 2.5. Hardware Testing 2.6. Signals
2.3. Functional Description x
2.3.1. Design Example Components 2.3.2. Reset Scheme 2.3.3. Clocking Scheme
2.3.1. Design Example Components x
2.3.1.1. Serial Lite III Streaming IP Core 2.3.1.2. Traffic Generator 2.3.1.3. Traffic Checker 2.3.1.4. Demo Control 2.3.1.5. Demo Management 2.3.1.6. Nios® V Processor Code
2.4. Simulation x
2.4.1. Testbench
2.5. Hardware Testing x
2.5.1. Design Setup 2.5.2. Error Details
3. Detailed Description for Stratix® V Serial Lite III Streaming Advanced Clocking Mode x
3.1. Features 3.2. Hardware and Software Requirements 3.3. Functional Description 3.4. Simulation 3.5. Hardware Testing 3.6. Signals
3.3. Functional Description x
3.3.1. Design Example Components 3.3.2. Reset Scheme 3.3.3. Clocking Scheme
3.3.1. Design Example Components x
3.3.1.1. Serial Lite III Streaming IP Core 3.3.1.2. Source User Clock - I/O PLL 3.3.1.3. Traffic Generator 3.3.1.4. Traffic Checker 3.3.1.5. Demo Control 3.3.1.6. Demo Management 3.3.1.7. Nios® V Processor Code
3.4. Simulation x
3.4.1. Testbench
3.5. Hardware Testing x
3.5.1. Design Setup 3.5.2. Error Details
1. Quick Start Guide
2. Detailed Description for Stratix® V Serial Lite III Streaming Standard Clocking Mode
3. Detailed Description for Stratix® V Serial Lite III Streaming Advanced Clocking Mode
A. Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide Archives
B. Document Revision History for the Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide

1.3.3. Presets

Standard presets allow instant entry of pre-selected parameter values in the IP and Example Design tabs. You can select the presets at the lower right window in the parameter editor.

The parameter values chosen for the presets belong to the group of supported Serial Lite III Streaming IP configurations for design example generation. You can select one of the presets available for your target device to quickly generate a design example without having to manually set each parameter in the IP tab and verifying that the parameter matches the supported configurations set.

Note: Only designs generated from the presets support hardware design examples.

There are two preset settings available in the library that support Duplex, Sink and Source modes:

  • Advanced Clocking Mode 2x10G
  • Standard Clocking Mode 2x10G
Table 3.  Parameter Settings for Stratix® V Design Example Presets
Presets Advanced Clocking Mode 2x10G Standard Clocking Mode 2x10G
Direction Duplex, Sink, and Source Duplex, Sink, and Source
Number of lanes 2 2
Meta frame length in words 200 200
Transceiver reference clock frequency (MHz) 644.53125 644.531187
Enable M20K ECC support ON and OFF ON and OFF
Clocking Mode Advanced clocking mode Standard clocking mode
Required user clock frequency (MHz) 150.8395522 146.484375
Transceiver data rate (Gbps) 10.3125 10.312499
Level Two Title