Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide
ID
683335
Date
4/09/2025
Public
1. Quick Start Guide
2. Detailed Description for Stratix® V Serial Lite III Streaming Standard Clocking Mode
3. Detailed Description for Stratix® V Serial Lite III Streaming Advanced Clocking Mode
A. Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide Archives
B. Document Revision History for the Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide
3.3.1.7. Nios® V Processor Code
The Nios® V processor controls the options exercised in the design example. The code also enables the configuration RAM (CRAM) bits for CRC-32 error injection support.
The design example sets the bit for channel 0 that connects to lane 0 in the design example. Therefore, CRC error injection is exercisable for lane 0 only. Refer to the Nios® V processor source code (demo_control.c) for information on setting bits for other channels.
The demo_control.c program Stratix® 10 H-tile and L-tile devices uses the control registers to dynamically toggle the rx_seriallpbken port on the Transceiver PHY block to change the TX to RX loopback from internal to external.