Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide
ID
683335
Date
4/09/2025
Public
1. Quick Start Guide
2. Detailed Description for Stratix® V Serial Lite III Streaming Standard Clocking Mode
3. Detailed Description for Stratix® V Serial Lite III Streaming Advanced Clocking Mode
A. Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide Archives
B. Document Revision History for the Serial Lite III Streaming Stratix® V FPGA IP Design Example User Guide
3.3.1.2. Source User Clock - I/O PLL
The I/O PLL generates a user clock for sourcing data into the Serial Lite III Streaming IP core when configured in Advanced Clocking Mode.