SDI Audio Intel® FPGA IP User Guide

Download
ID 683333
Date 6/26/2023
Public
Document Table of Contents
Document Table of Contents x
1. SDI Audio Intel FPGA IP Overview 2. SDI Audio Intel FPGA IP Getting Started 3. SDI Audio Intel FPGA IP Functional Description 4. SDI Audio Intel FPGA IP Parameters 5. SDI Audio Intel FPGA IP Interface Signals 6. SDI Audio Intel FPGA IP Registers 7. SDI Audio Intel FPGA IP User Guide Archives 8. Document Revision History for the SDI Audio Intel FPGA IP User Guide
1. SDI Audio Intel FPGA IP Overview x
1.1. Release Information 1.2. Performance and Resource Utilization
2. SDI Audio Intel FPGA IP Getting Started x
2.1. Instantiating the SDI Audio Intel FPGA IP Simulating the Testbench
3. SDI Audio Intel FPGA IP Functional Description x
3.1. SDI Audio Embed IP Core 3.2. SDI Audio Extract IP Core 3.3. SDI Clocked Audio Input IP Core 3.4. SDI Clocked Audio Output IP Core 3.5. AES Format 3.6. Avalon Streaming Interface Audio Interface
4. SDI Audio Intel FPGA IP Parameters x
4.1. SDI Audio Embed IP Core Parameters 4.2. SDI Audio Extract IP Core Parameters 4.3. SDI Clocked Audio Input IP Core Parameters 4.4. SDI Clocked Audio Output IP Core Parameters
5. SDI Audio Intel FPGA IP Interface Signals x
5.1. SDI Audio Embed IP Core Signals 5.2. SDI Audio Extract IP Core Signals 5.3. SDI Audio Clocked Input Signals 5.4. SDI Audio Clocked Output Signals 5.5. SDI Audio IP Register Interface Signals
6. SDI Audio Intel FPGA IP Registers x
6.1. SDI Audio Embed Registers 6.2. SDI Audio Extract Registers 6.3. SDI Clocked Audio Input Registers 6.4. SDI Clocked Audio Output Registers
1. SDI Audio Intel FPGA IP Overview
2. SDI Audio Intel FPGA IP Getting Started
3. SDI Audio Intel FPGA IP Functional Description
4. SDI Audio Intel FPGA IP Parameters
5. SDI Audio Intel FPGA IP Interface Signals
6. SDI Audio Intel FPGA IP Registers
7. SDI Audio Intel FPGA IP User Guide Archives
8. Document Revision History for the SDI Audio Intel FPGA IP User Guide

3.2. SDI Audio Extract IP Core

The SDI Audio Extract IP core accepts the SD-, HD-, and 3G-SDI from the SDI IP cores and extracts one channel pair of embedded audio.

The format of the embedded audio is in accordance with the following standards:

  • SMPTE272M-ABCD standard for SD-SDI
  • SMPTE299M standard for HD-SDI
  • SMPTE299M standard for 3G-SDI (provisional)

If you are extracting more than one channel pair, you must use multiple instances of the component. This IP core supports AES audio format for a 48 kHz sampling rate.

Figure 2. SDI Audio Extract IP Core Block Diagram

The SDI Audio Extract IP core consists of the following components:

  • An audio extraction core
  • A register interface block that provides support for an Avalon® memory-mapped interface control bus

The clock recovery block recreates a 64 × sample rate clock, which you can use to clock the audio output logic. As the component recreates this clock from a 200 MHz reference clock, the created clock may have a higher jitter than is desirable.

A digital PLL synchronizes this created clock to a 24 kHz reference source.

For the HD-SDI embedded audio, the 24 kHz reference source is the embedded clock phase information.

For the SD-SDI embedded audio, where the embedded clock phase data is not present, you can create the 24 kHz reference signal directly from the video clock.

Figure 3. Clock Recovery Block Diagram
Level Two Title

Did you find the information on this page useful?

Characters remaining:

Feedback Message