3.2. SDI Audio Extract IP Core
The format of the embedded audio is in accordance with the following standards:
- SMPTE272M-ABCD standard for SD-SDI
- SMPTE299M standard for HD-SDI
- SMPTE299M standard for 3G-SDI (provisional)
If you are extracting more than one channel pair, you must use multiple instances of the component. This IP core supports AES audio format for a 48 kHz sampling rate.
The SDI Audio Extract IP core consists of the following components:
- An audio extraction core
- A register interface block that provides support for an Avalon® memory-mapped interface control bus
The clock recovery block recreates a 64 × sample rate clock, which you can use to clock the audio output logic. As the component recreates this clock from a 200 MHz reference clock, the created clock may have a higher jitter than is desirable.
A digital PLL synchronizes this created clock to a 24 kHz reference source.
For the HD-SDI embedded audio, the 24 kHz reference source is the embedded clock phase information.
For the SD-SDI embedded audio, where the embedded clock phase data is not present, you can create the 24 kHz reference signal directly from the video clock.
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