4.2. SDI Audio Extract IP Core Parameters
|Async Audio Interface||On or Off||
Turn on to enable the Asynchronous output.
This mode supports an audio clock equal to or higher than 64 × sample rate.
|Parallel Audio Interface||On or Off||
Turn on to send AES data in parallel mode with a 32-bit parallel interface.
Requires Async Audio Interface to be turned on.
The actual audio sample rate is specified for serial data transmission. The equivalent audio sample rate in parallel mode matches the actual audio sample rate.
|Include SD-SDI 24-bit support||On or Off||
Enables the extra logic to recover the EDP ancillary packets from SD-SDI inputs.
|Channel status RAM||On or Off||
Turn on to store the received channel status data.
|Include error checking||On or Off||
Turn on to enable extra error-checking logic to use the error status register.
|Include status register||On or Off||
Turn on to enable extra logic to report the audio FIFO status on the fifo_status port or register.
|Include clock||On or Off||
Turn on to enable the logic to recover both a sample rate clock and a 64 × sample rate clock.
With HD-SDI inputs, the core generates the output by using the embedded clock phase information.
With SD-SDI inputs, the core generates this output by using the counters running on the 27 MHz video clock. This generation limits the SD-SDI embedded audio to being synchronous to the video.
|Include Avalon streaming interface||On or Off||
Turn on to include the SDI Clocked Audio Input IP core.
Turning on this parameter causes the Avalon streaming interface signals to appear at the top level. Otherwise, the audio input signals appear at the top level.
|Include Avalon® memory-mapped interface control interface||On or Off||
Turn on to include the Avalon® memory-mapped interface control interface.
Turning on this parameter causes the register interface signals to appear at the top level. Otherwise, the direct control interface signals appear at the top level.