SDI Audio Intel® FPGA IP User Guide

ID 683333
Date 6/26/2023
Document Table of Contents

5.4. SDI Audio Clocked Output Signals

Table 23.  SDI Audio Clocked Output Input and Output Signals
Signal Width Direction Description
aes_clk [0:0] Input Audio input clock.
aes_de [0:0] Output Audio data enable.
aes_ws [0:0] Output Audio word select.
aes_data [0:0] Output Audio data input in internal AES format.
Table 24.  SDI Audio Clocked Output Avalon-ST Audio SignalsThis table lists the Avalon streaming interface audio signals when you instantiate the SDI Audio Clocked Output IP core in Platform Designer (Standard).
Signal Width Direction Description
aud_clk [0:0] Input Clocked audio clock. All the audio input signals are synchronous to this clock.
aud_ready [0:0] Output Avalon streaming interface ready signal. Assert this signal when the device is able to receive data.
aud_valid [0:0] Input Avalon streaming interface valid signal. The core asserts this signal when it receives data.
aud_sop [0:0] Input Avalon streaming interface start of packet signal. The core asserts this signal when it is starting a new frame.
aud_eop [0:0] Input Avalon streaming interface end of packet signal. The core asserts this signal when it is ending a frame.
aud_data [23:0] Input Avalon streaming interface data bus. This bus transfers data.

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