SDI Audio Intel FPGA IP User Guide

Download PDF
ID 683333
Date 12/15/2021
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
Document Table of Contents x
1. SDI Audio Intel FPGA IP Overview 2. SDI Audio Intel FPGA IP Getting Started 3. SDI Audio Intel FPGA IP Functional Description 4. SDI Audio Intel FPGA IP Parameters 5. SDI Audio Intel FPGA IP Interface Signals 6. SDI Audio Intel FPGA IP Registers 7. SDI Audio Intel FPGA IP User Guide Archives 8. Document Revision History for the SDI Audio Intel FPGA IP User Guide
1. SDI Audio Intel FPGA IP Overview x
1.1. Release Information
2. SDI Audio Intel FPGA IP Getting Started x
2.1. Instantiating the SDI Audio Intel FPGA IP Simulating the Testbench
3. SDI Audio Intel FPGA IP Functional Description x
3.1. SDI Audio Embed IP Core 3.2. SDI Audio Extract IP Core 3.3. SDI Clocked Audio Input IP Core 3.4. SDI Clocked Audio Output IP Core 3.5. AES Format 3.6. Avalon-ST Audio Interface
4. SDI Audio Intel FPGA IP Parameters x
4.1. SDI Audio Embed Parameters 4.2. SDI Audio Extract Parameters 4.3. SDI Audio Clocked Audio Input Parameters 4.4. SDI Audio Clocked Audio Output Parameters
5. SDI Audio Intel FPGA IP Interface Signals x
5.1. SDI Audio Embed Signals 5.2. SDI Audio Extract Signals 5.3. SDI Audio Clocked Input Signals 5.4. SDI Audio Clocked Output Signals 5.5. SDI Audio IP Register Interface Signals
6. SDI Audio Intel FPGA IP Registers x
6.1. SDI Audio Embed Registers 6.2. SDI Audio Extract Registers 6.3. SDI Clocked Audio Input Registers 6.4. SDI Clocked Audio Output Registers
1. SDI Audio Intel FPGA IP Overview
2. SDI Audio Intel FPGA IP Getting Started
3. SDI Audio Intel FPGA IP Functional Description
4. SDI Audio Intel FPGA IP Parameters
5. SDI Audio Intel FPGA IP Interface Signals
6. SDI Audio Intel FPGA IP Registers
7. SDI Audio Intel FPGA IP User Guide Archives
8. Document Revision History for the SDI Audio Intel FPGA IP User Guide

6.1. SDI Audio Embed Registers

The following tables list the registers for the SDI Audio Embed IP core.

Table 25.  SDI Audio Embed Register Map

Bytes Offset

Name

00h

Audio Control Register

01h

Extended Control Register

02h

Video Status Register

03h

SD EDP Control Register

04h

Channel Status Control Registers (3:0)

05h

Channel Status Control Registers (7:4)

06h

Strip Control Register1

07h

Strip Status Register1

08h

Sine Channel 1 Frequency

09h

Sine Channel 2 Frequency

0Ah

Sine Channel 3 Frequency

0Bh

Sine Channel 4 Frequency

0Ch

Audio Status Register

0Dh-0Fh

Reserved

10h-3Fh

Channel Status RAM (0×00), (0×01), ... (0×2F)

Table 26.  SDI Audio Embed Registers

Bit

Name

Access

Description

Audio Control Register

7:0

Audio group enable

RW

Enables the embedding of each audio group. When working with HD-SDI or 3G-SDI video, this register also enables the embedding of the audio control packet when one or more audio groups are enabled.

The following bits correspond to the number of audio groups you specify:

  • Bit [1:0] = Audio group 1
  • Bit [3:2] = Audio group 2
  • Bit [5:4] = Audio group 3
  • Bit [7:6] = Audio group 4

Extended Control Register

2:0

Channel status RAM select

RW

When you specify the Channel Status RAM parameter to 2, this field selects the channel pair for the RAM written to by registers 10h to 3Fh. If you specify the Channel Status RAM parameter to 0 or 1, ignore this signal.

3

Unused

—

Reserved for future use.

4

Test sine generator enable

RW

When set to 1b, this bit ignores the audio inputs and uses the output of the sine generator as the data for each audio group.

6:5

Link AB Control

RW

This register applies only for 3G-SDI Level B standard.

Controls which link the ancillary data is embedded in.

  • 00b = No data is embedded
  • 01b = Data is embedded only in Link B.
  • 10b = Data is embedded only in Link A (default value).
  • 11b = Data is embedded in Link A and Link B at the same time.

When set to 11b, the IP core inserts new packets after any existing ancillary data on Link A and in the identical location on Link B.

If the packet distribution of existing ancillary data on Link B differs, existing packets may be corrupted. In these circumstances, Intel recommends you use two separate instances of the ancillary embedder.

7

Unused

—

Reserved for future use.

Video Status Register

7:0

Active channel

RO

Reports the detected video input standard.

  • Bits[7:5] = Picture structure code. Defined values for picture structure code are:
    • 001b = 486 or 576 line SD-SDI
    • 100b = 720 line HD-SDI
    • 101b = 1080 line HD-SDI
    • 010b = 1080 line 3G-SDI
    • 011b = 1080 line 3GA-SDI
    • 110b = 720 line 3GA-SDI
    • 111b = 720 line 3GB-SDI
  • Bit[4] = 0b—Interlace or segmented frame, 1b—Progressive.
  • Bits[3:0] = Frame rate code. Defined values for frame rate code (in Hz) are:
    • 0010b = 23.97
    • 0011b = 24
    • 0101b = 25
    • 0110b = 29.97
    • 0111b = 30
    • 1001b = 50
    • 1010b = 59.94
    • 1011b = 60

SD EDP Control Register

3:0

Enable SD EDP

RW

Enables the embedding of SD-SDI Extended Data Packets (EDP) for each audio group.

7:4

Enable SD ACP

RW

Enables the embedding of SD-SDI Audio Control Packets (ACP) for each audio group.

Channel Status Control Register

7:0

CS mode select

RW

When set to 00b, the core keeps the existing channel status data.

When set to 01b, the core replaces the channel status data with these default values:

  • Channel status byte 0: 0x8
  • Channel status byte 1: 0x02
  • Channel status byte 2–22: 0x00
  • Channel status byte 23: 0xDD

When set to 10b, the core replaces the data with the contents of the appropriate channel status RAM.

The following bits correspond to the number of audio groups you specify:

  • Bit [1:0] = Audio group 1
  • Bit [3:2] = Audio group 2
  • Bit [5:4] = Audio group 3
  • Bit [7:6] = Audio group 4

Strip Control Register

3:0

Strip enable

RW

Enables the removal of both ACP and ADP (and any SD-SDI EDP) for each of the four audio groups.

7:4

Unused

—

Reserved for future use.

Strip Status Register

3:0

Data packet present

RO

3:0

Reports which audio data groups are detected in the SDI stream.

When in 3G-SDI Level B mode, this register reports the presence of audio on Link A (Link B should be a duplicate).

7:4

Control packet present

RO

Reports which audio control groups are detected in the SDI stream.

When in 3G-SDI Level B mode, this register reports the presence of audio on Link A (Link B should be a duplicate).

Sine Channel n Frequency

7:0

Sine channel frequency

RW

Defines the frequency of the generated audio.

Audio Status Register

4

Frame lock RO Reports whether the video frame with the embedded audio is locked.

Channel Status RAM

7:0

Channel status data

WO

Write accesses within the address range 10h to 3Fh to the channel status RAM. This field returns the 24 bytes of channel status for X channels starting at address 10h to 27h, and the 24 bytes of channel status for Y channels starting at address 28h to 3Fh.

Related Information
1 The Intel® Quartus® Prime Pro Edition software SDI Audio Intel® FPGA IP does not support strip control and strip status.
Level Two Title